AM79Q4457J ETC1 [List of Unclassifed Manufacturers], AM79Q4457J Datasheet - Page 28

• Manufacturer Part Number: AM79Q4457J
• Description: Quad Subscriber Line Audio Processing Circuit-Non-Programmable (QSLAC-NP) Devices
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

Long-Frame Sync Mode
If each of the transmit (FSX
lap three or more negative-going transitions of PCLK,
the part operates in what is called Long-Frame Sync
mode. The time slot begins at the first point where both
frame sync and PCLK are High.
The beginning of a transmit time slot enables the DXA
output with the sign bit as the first output. It also drives
the TSCA output Low. The succeeding seven positive
clock transitions shift out the remainder of the data.
The eighth negative transition of PCLK or the end of
FSX, whichever comes later, tri-states DXA and turns
off TSCA. If FSX extends beyond the eighth PCLK
edge, the eighth bit is held at DXA. During the latter
part of each output period, the transmit data is held by
a weak driver in order to minimize bus contention if one
time slot starts before the preceding one ends.
The first negative PCLK transition after the beginning
of a receive time slot latches in the first data bit (sign
bit) from the DRA input. The succeeding seven nega-
tive clock transitions shift in the remainder of the data.
APPLICATIONS
The QSLAC-NP device family consists of two devices,
the Am79Q5457 device and the Am79Q4457 device.
The Am79Q5457 device is a four-channel Codec/Filter
device with eight frame synchronization inputs, two
per channel. Both the Am79Q4457 and Am79Q5457
d e v i c e s a r e A - l a w o r µ - l a w c o m p a t i b l e . T h e
Am79Q4457 device provides all the functions of the
Am79Q5457 device and the additional functions of se-
lecting transmit and receive gain levels and balance
networks on a per-channel basis.
If the application requires a fixed transmit and receive
gain level and one balance network, the Am79Q5457
device is ideal. If the application requires more than
one gain setting or balance network, the Am79Q4457
device is ideal. If full programmability of gain, fre-
quency response, balance impedance, input imped-
ance, and time slot assignment are required, then
the Am79Q02/021/031 Quad SLAC (QSLAC) device
is ideal.
The QSLAC-NP device performs the Codec/Filter func-
tion for four telephone lines. It interfaces to the tele-
phone lines through four Legerity SLIC devices as
shown in Figure 10 and Figure 11. The QSLAC-NP de-
vice may require an external buffer to drive transformer
SLICs.
Connection to a PCM back plane is implemented by
means of a simple buffer IC. See Figure 10 and Fig-
ure 11. Several QSLAC-NP devices can be tied to-
gether in one bus interfacing the back plane through
a single buffer. An intelligent bus interface chip is not
required because each QSLAC-NP device provides
its own buffer control (TSCA).
28
N
) frame sync pulses over-
Am79Q4457/5457 Data Sheet
SETTING GAIN LEVELS
Gain Settings for the Am79Q4457 Device
The possible transmit and receive gain levels are set
once for the four channels via three reference currents
and three reference voltages (see Figure 9a). The
three I
voltage so that a resistor placed from the output to
ground sets up a reference current in the device.
These reference currents are buffered and provided as
inputs to the 3-to-1 analog multiplexers, one per chan-
nel. One of three reference currents can be selected
for use by the transmit A/D converter. Each reference
current set up by the user corresponds to one transmit
gain setting. The transmit gain is a function of the input
resistor RTX and the reference resistor R
in Figure 9a and Table 2.
In much the same way, three reference voltages are
set up, one internally and two externally, as shown in
Figure 9a. These voltages are internally buffered and
provided to the 3-to-1 analog multiplexers, one per
channel. One of three reference voltages can be se-
lected and provided to the receive D/A converter for
use in decoding the data. Each reference voltage level
corresponds to a receive gain setting. The receive gain
is a function of the internally generated reference volt-
age V
shown in Figure 9a and Table 3.
One of two balance networks per channel is selected
via the serial control register. As shown in Figure 9a,
this is achieved by providing two inputs to the transmit
A/D converter and using a 2-to-1 analog multiplexer to
select the desired input.
See Figure 9. “b” represents the value of BNS1.
TGS2
0
0
1
1
REF1
REF
Transmit Gain Select 1 (TGS1) and
outputs are biased at the internal reference
and the scaled version V
Transmit Gain Select 2 (TGS2)
Table 2. Transmit Gain Select
(Am79Q4457 Device Only)
TGS1
0
1
0
1
Do Not Use
Gt
Gt
Gt
=
=
=
Gt1
Gt2
Gt3
=
=
=
A-to-D Gain
3 R
--------------------------- -
3
------------------------------------------------------------------- -
3
------------------------------------------------------------------- -
Rb
R
R REF3A
REF1
TX
REF2
REF2A
Rb TX
Rb TX
REF
or V
+
+
as shown
R
R REF3B
REF3
REF2B
, as