AM79Q4457J ETC1 [List of Unclassifed Manufacturers], AM79Q4457J Datasheet - Page 21

• Manufacturer Part Number: AM79Q4457J
• Description: Quad Subscriber Line Audio Processing Circuit-Non-Programmable (QSLAC-NP) Devices
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

Master Clock
Notes:
1. The PCM clock frequency must be an integer multiple of the frame sync frequency. The maximum allowable PCM clock
2. t
3. There is a special conflict detection circuitry that will prevent high-power dissipation from occurring when the DX pins of two
SWITCHING WAVEFORMS
Input and Output Waveforms for AC Tests
Master Clock Timing
No.
frequency is 4.096 MHz. The actual PCM clock rate is dependent on the number of channels allocated within a frame. The
minimum clock frequency is 256 kHz.
QSLAC-NP devices are tied together and one QSLAC-NP device starts to transmit before the other has gone into a
high-impedance state.
TSO
38
39
40
41
42
is defined as the time at which the output achieves the open circuit condition.
Symbol
A
t
t
t
t
MCR
MCF
MCH
MCL
MCY
Master Clock Accuracy
Rise Time of Clock
Fall Time of Clock
MCLK High Pulse Width
MCLK Low Pulse Width
0.45
2.4
V
IL
V
41
Parameter
IH
2.0
0.8
42
40
SLAC Products
Points
Test
38
2.0
0.8
Min
–100
97
97
39
Typ
Max
+100
15
15
19256A-015
20031A-005
Units
ppM
ns
ns
ns
ns
21