AM79C974KCW AMD [Advanced Micro Devices], AM79C974KCW Datasheet - Page 67
![no-image](/images/no-image-200.jpg)
AM79C974KCW
Manufacturer Part Number
AM79C974KCW
Description
PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AM79C974KCW.pdf
(153 pages)
- Current page: 67 of 153
- Download datasheet (833Kb)
accept writes to the APROM offsets within the
Am79C974 I/O resources map. Startup code in the sys-
tem BIOS can perform the PCI configuration accesses,
the IESRWE bit write, and the APROM writes.
Direct Access to the Microwire Interface
The user may directly access the Microwire port through
the EEPROM register, BCR19. This register contains
bits that can be used to control the Microwire interface
pins. By performing an appropriate sequence of I/O ac-
cesses to BCR19, the user can effectively write to and
read from the EEPROM. This feature may be used by a
system configuration utility to program hardware con-
figuration information into the EEPROM.
EEPROM-Programmable Registers
The following registers contain configuration informa-
tion that will be programmed automatically during the
EEPROM read operation:
1. I/O offsets 0h – Fh
2. BCR2
APROM locations
Miscellaneous Configuration
P R E L I M I N A R Y
Am79C974
3. BCR16
4. BCR17
5. BCR18
6. BCR21
If the PREAD bit (BCR19) is reset to ZERO and the
PVALID bit (BCR19) is reset to ZERO, then the
EEPROM read has experienced a failure and the con-
tents of the EEPROM programmable BCR register will
be set to default H_RESET values. The content of the
APROM locations, however, will not be cleared.
Note that accesses to the APROM I/O locations do not
directly access the Address EEPROM itself. Instead,
these accesses are routed to a set of shadow registers
on board the Am79C974 controller that are loaded with
a copy of the EEPROM contents during the automatic
read operation that immediately follows the H_RESET
operation.
register
not used in the Am79C974
controller
not used in the Am79C974
controller
Burst Size and Bus Control
Register
Not Used
AMD
67
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