AM79C974KCW AMD [Advanced Micro Devices], AM79C974KCW Datasheet - Page 36
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AM79C974KCW
Manufacturer Part Number
AM79C974KCW
Description
PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AM79C974KCW.pdf
(153 pages)
- Current page: 36 of 153
- Download datasheet (833Kb)
Basic Burst Write Cycles
All Am79C974 controller burst write transfers are of the
PCI command type Memory Write (type 7). AD[1:0] will
both be ZERO during the address phase indicating a lin-
ear burst order. All four byte enable signals will be ZERO
during the data phase as the Am79C974 controller al-
ways writes a full 32-bit word when in burst mode.
Figure 10 shows a typical burst write access. The
36
AMD
DEVSEL
FRAME
TRDY
IRDY
C/BE
REQ
GNT
PAR
CLK
AD
1
DEVSEL is sampled by the Am79C974 controller.
2
3
Figure 10. Burst Write Cycles
ADDR
0111
P R E L I M I N A R Y
4
Am79C974
DATA
PAR
5
0000
Am79C974 controller arbitrates for the bus, is granted
access, and writes four 32-bit words (DWORDs) from
system memory and then releases the bus. In this ex-
ample, the memory system extends the data phase of
the first access by one wait state. The following three
data phases take one clock cycle each, which is deter-
mined by the timing of TRDY.
PAR
6
DATA
7
DATA
PAR
8
DATA
PAR
9
PAR
10
18681A-14
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