ZL50052GAC ZARLINK [Zarlink Semiconductor Inc], ZL50052GAC Datasheet - Page 9

• Manufacturer Part Number: ZL50052GAC
• Description: 8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (32 Mbps), and 16 Inputs and 16 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Pin Description
Device Timing
Pin Name
FP8o
C16o
FP8i
C8o
C8i
Coordinates
Package
ZL50052
(196 ball
PBGA)
M10
P10
N10
N11
M9
Master Clock (5 V Tolerant Schmitt-Triggered Input)
This pin accepts an 8.192 MHz clock. The internal frame boundary is aligned
with the clock falling or rising edge, as controlled by the C8IPOL bit in the
Control Register. Input data on both the Backplane and Local sides (BSTi0-7
and LSTi0-7) must be aligned to this clock and the accompanying input frame
pulse, FP8i.
Frame Pulse Input (5 V Tolerant Schmitt-Triggered Input)
When the Frame Pulse Width bit (FPW) of the Control Register is LOW
(default), this pin accepts a 122 ns-wide frame pulse. When the FPW bit is
HIGH, this pin accepts a 244 ns-wide frame pulse. The device will
automatically detect whether an ST-BUS or GCI-Bus style frame pulse is
applied. Input data on both the Backplane and Local sides (BSTi0-7 and
LSTi0-7) must be aligned to this frame pulse and the accompanying input
clock, C8i.
C8o Output Clock (5 V Tolerant Three-state Output)
This pin outputs an 8.192 MHz clock generated within the device. The clock
falling edge or rising edge is aligned with the output frame boundary
presented on FP8o; this edge polarity alignment is controlled by the COPOL
bit of the Control Register. Output data on both the Backplane and Local
sides (BSTo0-7 and LSTo0-7) will be aligned to this clock and the
accompanying output frame pulse, FP8o.
Frame Pulse Output (5 V Tolerant Three-state Output)
When the Frame Pulse Width bit (FPW) of the Control Register is LOW
(default), this pin outputs a 122 ns-wide frame pulse. When the FPW bit is
HIGH, this pin outputs a 244 ns-wide frame pulse. The frame pulse, running
at 8 kHz rate, will have the same format (ST-BUS or GCI-Bus) as the input
frame pulse (FP8i). Output data on both the Backplane and Local sides
(BSTo0-7 and LSTo0-7) will be aligned to this frame pulse and the
accompanying output clock, C8o.
C16o Output Clock (5 V Tolerant Three-state Output)
This pin outputs a 16.384 MHz clock generated within the device. The clock
falling edge or rising edge is aligned with the output frame boundary
presented on FP16o; this edge polarity alignment is controlled by the COPOL
bit of the Control Register. Output data on both the Backplane and Local
sides (BSTo0-7 and LSTo0-7) will be aligned to this clock and the
accompanying output frame pulse, FP16o.
Zarlink Semiconductor Inc.
ZL50052
9
Description
Data Sheet