ZL50052GAC ZARLINK [Zarlink Semiconductor Inc], ZL50052GAC Datasheet - Page 42

• Manufacturer Part Number: ZL50052GAC
• Description: 8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (32 Mbps), and 16 Inputs and 16 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

13.6
Addresses 00A3
8 Backplane Output Advancement Registers (BOAR0 to BOAR7) allow users to program the output advancement
for output data streams BSTo0 to BSTo7. The possible adjustment is -1 (7.6 ns), -2 (15 ns) or -3 (23 ns) cycles of
the internal system clock (131.072 MHz).
The BOAR0 to BOAR7 registers are configured as follows:
13.6.1
The binary value of these two bits indicates the amount of offset that a particular stream output can be advanced
with respect to the output frame boundary. When the advancement is 0, the serial output stream has the normal
alignment with the generated frame pulse FP8o.
Backplane Output Advancement Registers (BOAR0 - BOAR7)
(where n = 0 to 7)
Backplane Output Advancement Bits 1-0 (BOA1-BOA0)
BOARn Bit
15:2
1:0
H
Table 20 - Backplane Output Advancement (BOAR) Programming Table
to 00AA
Table 19 - Backplane Output Advancement Register (BOAR) Bits
H
Backplane Output Advancement
Clock Rate 131.072 MHz
Reserved
-2 cycles (~15 ns)
-3 cycles (~23 ns)
BOA[1:0]
-1 cycle (~7.6 ns)
Name
0 (Default)
Zarlink Semiconductor Inc.
ZL50052
Reset
Value
0
0
42
Reserved
Must be set to 0 for normal operation
Backplane Output Advancement Value
Advancement Bits
BOA1
Corresponding
0
0
1
1
Description
BOA0
0
1
0
1
Data Sheet