ZL50052GAC ZARLINK [Zarlink Semiconductor Inc], ZL50052GAC Datasheet - Page 41

• Manufacturer Part Number: ZL50052GAC
• Description: 8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (32 Mbps), and 16 Inputs and 16 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

13.5
Addresses 0083
8 Local Output Advancement Registers (LOAR0 to LOAR7) allow users to program the output advancement for
output data streams LSTo0 to LSTo7. The possible adjustment is -1 (7.6 ns), -2 (15 ns) or -3 (23 ns) cycles of the
internal system clock (131.072 MHz).
The LOAR0 to LOAR7 registers are configured as follows:
13.5.1
The binary value of these two bits indicates the amount of offset that a particular stream output can be advanced
with respect to the output frame boundary. When the advancement is 0, the serial output stream has the normal
alignment with the generated frame pulse FP8o.
Local Output Advancement Registers (LOAR0 to LOAR7)
(where n = 0 to 7)
Local Output Advancement Bits 1-0 (LOA1-LOA0)
LOARn Bit
15:2
1:0
H
to 008A
Table 18 - Local Output Advancement (LOAR) Programming Table
Table 17 - Local Output Advancement Register (LOAR) Bits
H
.
Local Output Advancement
Clock Rate 131.072 MHz
Reserved
-2 cycles (~15 ns)
-3 cycles (~23 ns)
LOA[1:0]
-1 cycle (~7.6 ns)
Name
0 (Default)
Zarlink Semiconductor Inc.
ZL50052
Reset
Value
0
0
41
Reserved
Must be set to 0 for normal operation
Local Output Advancement Value
Advancement Bits
LOA1
Corresponding
0
0
1
1
Description
LOA0
0
1
0
1
Data Sheet