ZL50052GAC ZARLINK [Zarlink Semiconductor Inc], ZL50052GAC Datasheet - Page 51

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ZL50052GAC

Manufacturer Part Number
ZL50052GAC
Description
8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (32 Mbps), and 16 Inputs and 16 Outputs
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
Local and Backplane Data Timing
1
2
3
4
5
32.768 Mbps
32.768 Mbps
L/BSTo0-7
L/BSTi0-7
Note *: CK_int is the internal clock signal of 131.072 MHz.
CK_int *
CK_int *
Local/Backplane Input Data Sampling Point
Local/Backplane Serial Input Set-up Time
Local/Backplane Serial Input Hold Time
Output Frame Boundary Offset
Local/Backplane Serial Output Delay
FP8o
FP8i
C8o
C8i
Characteristic
Figure 19 - ST-BUS Local/Backplane Data Timing Diagram (32 Mbps)
Ch511
Bit1
2
Ch511
Bit1
1
Ch511
Bit0
0
Zarlink Semiconductor Inc.
t
ZL50052
OFBOS
Ch0
Bit7
7
t
SOD32
t
t
t
OFBOS
Sym.
t
t
SOD32
IDS32
SIS32
SIH32
51
t
t
SIS32
IDS32
t
SIH32
Ch0
Bit6
6
Min.
20
2
2
Typ.
Ch0
Bit5
5
23
7
Max.
9.5
4.5
26
Ch0
Bit4
4
Units
ns
ns
ns
ns
ns
Ch0
Bit3
3
With
SMPL_MODE =
0 (3/4-bit
sampling) and
zero offset.
With respect to
Min. Input Data
Sampling Point
With respect to
Max. Input Data
Sampling Point
C
These numbers
are referencing
output frame
boundary.
L
= 50 pF
Data Sheet
Notes
Bit2
Ch0
2

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