ZL50052GAC ZARLINK [Zarlink Semiconductor Inc], ZL50052GAC Datasheet - Page 55

no-image

ZL50052GAC

Manufacturer Part Number
ZL50052GAC
Description
8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (32 Mbps), and 16 Inputs and 16 Outputs
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
Non-Multiplexed Microprocessor Port Timing
Note 1:
Note 2:
10
12
11
1
2
3
4
5
6
7
8
9
CS setup from DS falling
R/W setup from DS falling
Address setup from DS falling
CS hold after DS rising
R/W hold after DS rising
Address hold after DS rising
Data setup from DTA Low on Read
Data hold on read
Data setup on write
Data hold on write
Acknowledgment Delay:
Acknowledgment Hold Time
High Impedance is measured by pulling to the appropriate rail with R
C
There must be a minimum of 30 ns between CPU accesses, to allow the device to recognize the accesses as separate (i.e., a
minimum of 30 ns must separate the de-assertion of DTA (to high) and the assertion of CS and/or DS to initiate the next
access).
Reading/Writing Registers
Reading/Writing Memory
L
.
Characteristics
Zarlink Semiconductor Inc.
Sym.
t
t
t
t
t
t
t
t
t
t
t
t
RWS
RWH
WDS
WDH
RDH
CSS
ADS
CSH
ADH
RDS
AKD
AKH
ZL50052
55
Min.
12
0
9
9
0
9
9
5
9
9
L
Typ.
, with timing corrected to cancel time taken to discharge
Max.
4.5
88
80
11
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Memory Read
Register Read
C
C
R
Note 1
C
C
C
R
Note 1
Test Conditions
L
L
L
L
L
L
L
= 60 pF,
= 60 pF
= 1 k
= 60 pF
= 60 pF
= 1 k,
= 60 pF,
Data Sheet

Related parts for ZL50052GAC