ZL50015GAC ZARLINK [Zarlink Semiconductor Inc], ZL50015GAC Datasheet - Page 61

• Manufacturer Part Number: ZL50015GAC
• Description: Enhanced 1 K Digital Switch with Stratum 4E DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Note: [n] denotes output offset frame pulse from 0 to 2.
15 - 11
9 - 2
1 - 0
External Read/Write Address: 0005
Bit
Reset Value: 0000
15
10
0
14
0
FOF[n]OFF7 - 0
FOF[n]C1 - 0
13
Unused
FP19EN
0
Name
H
12
0
11
0
Reserved. In normal functional mode, these bits MUST be set to zero.
19.44 MHz Frame Pulse Output Enable. (For FPo_OFF2 only)
This bit is a reserved bit for FPo_OFF0 and FPo_OFF1, and MUST be set to
zero.
When this bit is high, FPo_OFF2 is negative frame pulse output corresponding to
19.44 MHz without channel offset.
When this bit is low, FPo_OFF2 is output frame pulse with channel offset.
FPo_OFF[n] Channel Offset
The binary value of these bits refers to the channel offset from original frame bound-
ary. Permitted channel offset values depend on bits 1-0 of this register.
FPo_OFF[n] Control bits
Table 22 - FPo_OFF[n] Register (FPo_OFF[n]) Bits
FOF[n]C
FP19
H
EN
10
1-0
00
01
10
11
- 0007
FOF[n]
OFF7
H
9
Data Rate
(Mbps)
16.384
2.048
4.096
8.192
FOF[n]
OFF6
Zarlink Semiconductor Inc.
8
ZL50015
one 4.096 MHz clock
one 8.192 MHz clock
one 16.384 MHz clock
one 16.384 MHz clock
FOF[n]
OFF5
Pulse Cycle Width
7
61
FPo_OFF[n]
FOF[n]
OFF4
6
Description
FOF[n]
OFF3
5
FOF[n]
FOF[n]OFF7 - 0
OFF2
Channel Offset
4
Permitted
0 - 127
0 - 255
0 - 31
0 - 63
FOF[n]
OFF1
3
FOF[n]
OFF0
2
Polarity
FPO0P
FPO1P
FPO2P
FPO2P
Control
FOF[n]
Data Sheet
C1
1
FPO0POS
FPO1POS
FPO2POS
FPO2POS
Position
Control
FOF[n]
C0
0