ZL50015GAC ZARLINK [Zarlink Semiconductor Inc], ZL50015GAC Datasheet - Page 16

• Manufacturer Part Number: ZL50015GAC
• Description: Enhanced 1 K Digital Switch with Stratum 4E DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

D9, E8, C8,
E9, D8, B8,
PBGA Pin
G15, G14,
E15, F14
Number
C12
B14
D7
E7
LQFP Pin
161, 164,
159, 163,
102, 106,
166, 168
Number
165, 167
110, 112
149
148
REF_FAIL0 - 3
Pin Name
REF0 - 3
FPo0 - 3
OSCo
OSCi
Zarlink Semiconductor Inc.
Oscillator Clock Output (3.3 V Output)
If OSC_EN = ‘1’, this pin should be connected to a 20 MHz crystal
(see Figure 23 on page 90) or left unconnected if a clock oscillator
is connected to OSCi pin under normal operation (see Figure 24
on page 91). If OSC_EN = 0, this pin MUST be left unconnected.
Oscillator Clock Input (3.3 V Input)
If OSC_EN = ‘1’, this pin should be connected to a 20 MHz crystal
(see Figure 23 on page 90) or to a clock oscillator under normal
operation (see Figure 24 on page 91). If OSC_EN = 0, this pin
MUST be driven high or low by connecting either to V
ground.
DPLL Reference Inputs 0 to 3 (5 V-Tolerant Schmitt-Triggered
Inputs)
If the device is in Master mode, these input pins accept 8 kHz,
1.544 MHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz or
19.44 MHz timing references independently. One of these inputs is
defined as the preferred or forced input reference for the DPLL.
The Reference Change Control Register (RCCR) selects the
control of the preferred reference.These pins are ignored if the
device is in slave mode unless SLV_DPLLEN (bit 13) in the
Control Register (CR) is set. When these input pins are not in use,
they MUST be driven high or low by connecting either to V
to ground.
Failure Indication for DPLL References 0 to 3 (5 V-Tolerant
Three-state Outputs)
These output pins are used to indicate input reference failure when
the device is in master mode.
If REF0 fails, REF_FAIL0 will be driven high.
If REF1 fails, REF_FAIL1 will be driven high.
If REF2 fails, REF_FAIL2 will be driven high.
If REF3 fails, REF_FAIL3 will be driven high.
If the device is in slave mode, these pins are driven low, unless
SLV_DPLLEN (bit 13) in the Control Register (CR) is set.
ST-BUS/GCI-Bus Frame Pulse Outputs 0 to 3 (5 V-Tolerant
Three-state Outputs)
FPo0: 8 kHz frame pulse corresponding to the 4.096 MHz output
clock of CKo0.
FPo1: 8 kHz frame pulse corresponding to the 8.192 MHz output
clock of CKo1.
FPo2: 8 kHz frame pulse corresponding to 16.384 MHz output
clock of CKo2.
FPo3: Programmable 8 kHz frame pulse corresponding to
4.096 MHz, 8.192 MHz, 16.384 MHz, or 32.768 MHz output clock
of CKo3.
In Divided Slave modes, the frame pulse width of FPo0 - 3 cannot
be narrower than the input frame pulse (FPi) width.
ZL50015
16
Description
Data Sheet
DD_IO
DD_IO
or to
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