ZL50015GAC ZARLINK [Zarlink Semiconductor Inc], ZL50015GAC Datasheet - Page 56

• Manufacturer Part Number: ZL50015GAC
• Description: Enhanced 1 K Digital Switch with Stratum 4E DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

15 - 9
External Read/Write Address: 0001
Reset Value: 0000
3 - 1
Bit
8
7
6
5
4
15
0
14
0
STIO_PD_
RBEREN
TBEREN
BPD2 - 0
Unused
Unused
Name
BDL
EN
H
13
0
12
0
Reserved. In normal functional mode, these bits MUST be set to zero.
STio Pull-down Enable
When this bit is low, the pull-down resistors on all STio pads will be disabled.
When this bit is high, the pull-down resistors on all STio pads will be enabled.
Reserved. In normal functional mode, these bits MUST be set to zero.
Used in this bi-directional mode.
Bi-directional Control for Streams 0-15
PRBS Receiver Enable
When this bit is low, all the BER receivers are disabled. To enable any BER receivers,
this bit MUST be high.
PRBS Transmitter Enable
When this bit is low, all the BER transmitters are disabled. To enable any BER
transmitters, this bit MUST be high.
Block Programming Data
These bits refer to the value to be loaded into the connection memory, whenever the
memory block programming feature is activated. After the MBPE bit in the Control
Register is set to high and the MBPS bit in this register is set to high, the contents of
the bits BPD2 - 0 are loaded into bits 2 - 0 of the Connection Memory Low. Bits 15 - 3
of the Connection Memory Low and bits 15 - 0 of Connection Memory High are
zeroed.
Table 18 - Internal Mode Selection Register (IMS) Bits
11
0
H
10
0
9
0
Zarlink Semiconductor Inc.
PD_EN
STIO_
BDL
0
1
8
ZL50015
56
7
0
STio0-15 are bi-directional
STi0-15 tied low internally
bi-directional operation:
STio0 - 15 Operation
STio0-15 are outputs
STi0-15 are inputs
normal operation:
Description
BDL
6
RBER
EN
5
TBER
EN
4
BPD
3
2
BPD
2
1
BPD
1
0
Data Sheet
MBPS
0