82V3001 IDT [Integrated Device Technology], 82V3001 Datasheet - Page 7

• Manufacturer Part Number: 82V3001
• Description: WAN PLL WITH SINGLE REFERENCE INPUT
• Manufacturer: IDT [Integrated Device Technology]

IDT82V3001A WAN PLL WITH SINGLE REFERENCE INPUT
2
Table - 1 Pin Description
HOLDOVER (CMOS) O
MODE_sel1
MODE_sel0
FREERUN
NORMAL
FLOCK
TIE_en
F_sel1
F_sel0
OSCo
LOCK
TCLR
Name
OSCi
C32o
RST
V
Fref
V
DD
SS
PIN DESCRIPTION
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) I
Power
Power
Type
I
I
I
I
I
I
I
I
I
12, 18, 27,
13, 19, 26,
Number
38, 47
37, 48
Pin
49
50
10
56
45
44
52
46
51
25
5
9
2
1
4
3
Ground.
0 V. All V
Positive Supply Voltage.
All V
Oscillator Master Clock.
This pin is left unconnected.
Oscillator Master Clock.
This pin is connected to a clock source.
Reference Input.
This is the input reference source (falling edge) used for synchronization. One of three possible frequencies (8 kHz, 1.544
MHz, or 2.048 MHz) may be used. The Fref pin is internally pulled up to V
Input Frequency Select 1.
This input, in conjunction with F_sel0, determines which of three possible frequencies (8 kHz, 1.544 MHz, or 2.048 MHz )
may be input to the Reference Input.
Input Frequency Select 0.
See above.
Mode/Control Select 1.
This input, in conjunction with MODE_sel0, determines the operation mode of the IDT82V3001A (Normal, Holdover or
Freerun) . The logic level at this input is gated in by the rising edge of F8o. This pin is internally pulled down to V
Table -
Mode/Control Select 0.
See above. The logic level at this input is gated in by the rising edge of F8o. This pin is internally pulled down to V
Reset Input.
A logic low at this pin resets the IDT82V3001A. To ensure proper operation, the device must be reset after the frequency
of the input reference is changed and power-up. The RST pin should be held low for a minimum of 300 ns. While the RST
pin is low, all framing and clock outputs are at logic high.
TIE Circuit Reset.
Logic low at this input resets the TIE (Time Interval Error) control block, resulting in a realignment of output phase with
input phase. The TCLR pin should be held low for a minimum of 300 ns. This pin is internally pulled up to V
TIE Enable.
A logic high at this pin enables the TIE control block while a logic low at this pin disables the TIE control block. The logic
level at this input is gated in by the rising edge of F8o. This pin is internally pulled down to V
Fast Lock Mode.
Set high to allow the DPLL to quickly lock to the input reference (less than 500 ms locking time).
Lock Indicator.
This output goes high when the DPLL is frequency locked to the input reference.
Holdover Indicator.
This output goes to a logic high whenever the DPLL goes into Holdover Mode.
Normal Indicator.
This output goes to a logic high whenever the DPLL goes into Normal Mode.
Freerun Indicator.
This output goes to a logic high whenever the DPLL goes into Freerun Mode.
Clock 32.768 MHz.
This output is a 32.768 MHz clock used for ST-BUS operation.
DD
2.
pins should be connected to +3.3 V nominal.
SS
pins should be connected to the ground.
7
Description
INDUSTRIAL TEMPERATURE RANGE
DD
.
ss
.
DD
.
SS
SS
. See
.