82V3001 IDT [Integrated Device Technology], 82V3001 Datasheet - Page 13

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82V3001

Manufacturer Part Number
82V3001
Description
WAN PLL WITH SINGLE REFERENCE INPUT
Manufacturer
IDT [Integrated Device Technology]
Datasheet

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IDT82V3001A WAN PLL WITH SINGLE REFERENCE INPUT
applying a logic low pulse to the TCLR pin. The reset pulse should be at
least 300 ns.
time periods and then turns back to Normal Mode, the TIE Control
Circuit should not be enabled. This will prevent undesired accumulated
3.5
The phase difference in the Storage Circuit can be cleared by
When the IDT82V3001A primarily enters Holdover Mode for short
As shown in
DPLL BLOCK
Figure -
8, the DPLL Block consists of a Phase Detector,
Previous Fref
Current Fref
Time = 0.00 s
Time = 0.25 s
Time = 0.50 s
Time = 0.75 s
Time = 1.0 s
Time = 1.25 s
Time = 1.50 s
Time = 1.75 s
Previous Fref
Current Fref
Time = 0.00 s
Time = 0.25 s
Time = 0.50 s
Time = 0.75 s
Time = 1.0 s
Time = 1.25 s
Time = 1.50 s
Time = 1.75 s
Figure - 7 State Switch with TIE Control Block Disabled
Figure - 6 State Switch with TIE Control Block Enabled
13
phase change between the input and output.
state switching, the phase of the output signal will align with that of the
new reference. The phase slope limited to 5 ns per 125 µs.
shows the phase transient resulting from a state switch with the TIE
Control Block disabled.
a Limiter, a Loop Filter, a Digital Control Oscillator and Dividers.
If the TIE Control Block is disabled manually or automatically during
Output Clock
Output Clock
Input Clock
Input Clock
INDUSTRIAL TEMPERATURE RANGE
Figure - 7

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