82V3001 IDT [Integrated Device Technology], 82V3001 Datasheet

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... Holdover frequency accuracy of 0.025 ppm • Phase slope of 5 ns/125 µs DESCRIPTION The IDT82V3001A is a WAN PLL with single reference input. It contains a Digital Phase-Locked Loop (DPLL), which generates ST-BUS clocks and framing signals that are phase locked to a 2.048 MHz, 1.544 MHz or 8 kHz input reference ...

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... IDT82V3001A WAN PLL WITH SINGLE REFERENCE INPUT FUNCTIONAL BLOCK DIAGRAM OSCi OSCo OSC Fref FLOCK TDI TMS JTAG TRST TCK TDO RST TIE_en MODE_sel1 TCLR Virtual TIE Control Reference Block Invalid Input Signal Detection Feedback Signal State Control Circuit ...

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... IDT82V3001A WAN PLL WITH SINGLE REFERENCE INPUT 1 IDT82V3001A PIN CONFIGURATION........................................................................................................................... 6 2 PIN DESCRIPTION ........................................................................................................................................................ 7 3 FUNCTIONAL DESCRIPTION..................................................................................................................................... 10 3.1 State Control Circuit............................................................................................................................................. 10 3.1.1 Normal Mode ............................................................................................................................................11 3.1.2 Fast Lock Mode ........................................................................................................................................ 11 3.1.3 Holdover Mode ......................................................................................................................................... 11 3.1.4 Freerun Mode ........................................................................................................................................... 12 3.2 Frequency Select Circuit...................................................................................................................................... 12 3.3 Invalid Input Signal Detection .............................................................................................................................. 12 3.4 TIE Control Block................................................................................................................................................. 12 3.5 DPLL Block .......................................................................................................................................................... 13 3.5.1 Phase Detector (PHD) .............................................................................................................................. 14 3 ...

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... IDT82V3001A WAN PLL WITH SINGLE REFERENCE INPUT Figure - 1 Block Diagram .................................................................................................................................................. 2 Figure - 2 IDT82V3001A SSOP56 Package Pin Assignment........................................................................................... 6 Figure - 3 State Control Block......................................................................................................................................... 10 Figure - 4 State Control Diagram.................................................................................................................................... 11 Figure - 5 TIE Control Circuit Diagram ........................................................................................................................... 12 Figure - 6 State Switch with TIE Control Block Enabled................................................................................................. 13 Figure - 7 State Switch with TIE Control Block Disabled ................................................................................................ 13 Figure - 8 DPLL Block Diagram ...

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... IDT82V3001A WAN PLL WITH SINGLE REFERENCE INPUT Table - 1 Pin Description .................................................................................................................................................. 7 Table - 2 Operating Modes and Status...........................................................................................................................10 Table - 3 Input Reference Frequency Selection ............................................................................................................. 12 Table - 4 Absolute Maximum Ratings**.......................................................................................................................... 18 Table - 5 Recommended DC Operating Conditions** .................................................................................................... 18 Table - 6 DC Electrical Characteristics** ........................................................................................................................ 18 Table - 7 Performance.................................................................................................................................................... 19 Table - 8 Intrinsic Jitter Unfiltered................................................................................................................................... 19 Table - 9 C1.5o (1.544 MHz) Intrinsic Jitter Filtered....................................................................................................... 20 Table - 10 C2o (2 ...

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... Figure - 2 IDT82V3001A SSOP56 Package Pin Assignment 6 INDUSTRIAL TEMPERATURE RANGE TIE_en 56 IC2 55 IC1 54 IC0 53 HOLDOVER 52 51 FREERUN 50 OSCi 49 OSCo NORMAL 46 45 FLOCK LOCK 44 43 ...

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... I 1 See above. The logic level at this input is gated in by the rising edge of F8o. This pin is internally pulled down to V Reset Input. A logic low at this pin resets the IDT82V3001A. To ensure proper operation, the device must be reset after the frequency I 4 RST of the input reference is changed and power-up ...

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... IDT82V3001A WAN PLL WITH SINGLE REFERENCE INPUT Table - 1 Pin Description (Continued) Pin Name Type Number Clock 16.384 MHz. C16o (CMOS This output is a 16.384 MHz clock used for ST-BUS operation. Clock 8.192 MHz. C8o (CMOS This output is an 8.192 MHz clock used for ST-BUS operation. ...

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... IDT82V3001A WAN PLL WITH SINGLE REFERENCE INPUT Table - 1 Pin Description (Continued) Pin Name Type Number 11, Internal Connection 21, 22, 34 Internal Use. These pins should be left open when in normal operation. 35, 43 INDUSTRIAL TEMPERATURE RANGE Description 9 ...

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... See Figure - 1. The detail is described in the following sections. 3.1 STATE CONTROL CIRCUIT The State Control Circuit is an important part of the IDT82V3001A. As shown in Figure - 3, the State Control Circuit outputs signals to enable/disable the TIE Control Block and control the operation mode of the DPLL Block based on MODE_sel0 and MODE_sel1 and TIE_en pins ...

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... NORMAL pin to high. 3.1.2 FAST LOCK MODE Fast Lock Mode is a submode of Normal Mode used to allow the IDT82V3001A to lock to a reference more quickly than Normal Mode will do. Typically, the DPLL will lock to the input reference within 500 ms if the FLOCK pin is high. Reset * ...

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... When the input reference returns to normal, the DPLL will return to Normal Mode. In Holdover Mode, the output signal of the IDT82V3001A is based on the output signal prior to entering Holdover Mode. The "OSC" ...

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... TCLR pin. The reset pulse should be at least 300 ns. When the IDT82V3001A primarily enters Holdover Mode for short time periods and then turns back to Normal Mode, the TIE Control Circuit should not be enabled. This will prevent undesired accumulated ...

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... IDT82V3001A WAN PLL WITH SINGLE REFERENCE INPUT Fraction_T1 Fraction_C6 Loop Filter 3.5.1 PHASE DETECTOR (PHD) In Normal Mode, the Phase Detector compares the virtual reference signal from the TIE Control Circuit with the feedback signal from the Frequency Select Circuit, and outputs an error signal corresponding to the phase difference between the two ...

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... Rise & Fall Time:10 ns (0. pF) Duty Cycle: 40% to 60% The output clock should be connected directly (not AC coupled) to INDUSTRIAL TEMPERATURE RANGE the OSCi input of the IDT82V3001A, and the OSCo output should be left open as shown in Figure - 9. IDT82V3001A OSCi OSCo ...

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... Intrinsic jitter is usually measured with various band limiting filters depending on the applicable standards. In the IDT82V3001A, the intrinsic Jitter is limited to less than 0. the 2.048 MHz and 1.544 MHz clocks. 4.2 ...

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... In the case of the IDT82V3001A, the output signal phase continuity is maintained to within ± the instance (over one frame) of all mode changes. The total phase shift, depending on the type of mode change, may accumulate up to 200 ns over many frames ...

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... IDT82V3001A WAN PLL WITH SINGLE REFERENCE INPUT 5 TEST SPECIFICATIONS ** Table - 4 Absolute Maximum Ratings Rating Power Supply Voltage Voltage on Any Pin with Respect to Ground Package Power Dissipation Storage Temperature Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...

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... IDT82V3001A WAN PLL WITH SINGLE REFERENCE INPUT 5.1 AC ELECTRICAL CHARACTERISTICS Table - 7 Performance Description Freerun Mode accuracy with OSCi ppm Freerun Mode accuracy with OSCi at : ±32 ppm Freerun Mode accuracy with OSCi at : ±100 ppm Holdover Mode accuracy with OSCi ppm Holdover Mode accuracy with OSCi at : ±32 ppm Holdover Mode accuracy with OSCi at : ± ...

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... IDT82V3001A WAN PLL WITH SINGLE REFERENCE INPUT Table - 9 C1.5o (1.544 MHz) Intrinsic Jitter Filtered Description Intrinsic jitter ( 100 kHz filter) Intrinsic jitter ( kHz filter) Intrinsic jitter (8 kHz to 40 kHz filter) Intrinsic jitter ( kHz filter) Table - 10 C2o (2.048 MHz) Intrinsic Jitter Filtered ...

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... IDT82V3001A WAN PLL WITH SINGLE REFERENCE INPUT Table - 13 2.048 MHz Input to 2.048 MHz Output Jitter Transfer Description Jitter at output for 1 Hz@3.00 UIpp input Jitter at output for 1 Hz@3.00 UIpp input with 100 Hz filter Jitter at output for 3 Hz@2.33 UIpp input Jitter at output for 3 Hz@2.33 UIpp input with 100 Hz filter Jitter at output for 5 Hz@2 ...

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... IDT82V3001A WAN PLL WITH SINGLE REFERENCE INPUT Table - 16 2.048 MHz Input Jitter Tolerance Description Jitter tolerance for 1 Hz input Jitter tolerance for 5 Hz input Jitter tolerance for 20 Hz input Jitter tolerance for 300 Hz input Jitter tolerance for 400 Hz input Jitter tolerance for 700 Hz input ...

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... IDT82V3001A WAN PLL WITH SINGLE REFERENCE INPUT 6 TIMING CHARACTERISTICS Table - 17 Timing Parameter Measurement Voltage Levels Parameter Rise and Fall Threshold Voltage High HM V Rise and Fall Threshold Voltage Low LM Notes: 1. Voltages are with respect to ground (V ) unless otherwise stated Supply voltage and operating temperature are as per Recommended Operating Conditions. ...

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... IDT82V3001A WAN PLL WITH SINGLE REFERENCE INPUT Table - 18 Input / Output Timing (Continued) Parameter Description t C2o pulse width high or low C2W t C4o pulse width high or low C4W t C8o pulse width high or low C8W t C16o pulse width high or low C16WL t C32o pulse width high ...

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... IDT82V3001A WAN PLL WITH SINGLE REFERENCE INPUT F8o F0o F16o F32o C32o C16o C8o t C4W C4o C2o t C6W C6o C3o C1.5o t F0WL t F16WL t F16S t F32WL t F32S t C32WH t C16WL t t C8W C8W t C4W t C2W t C6W t C3W t C15W Figure - 12 Output Timing 1 25 INDUSTRIAL TEMPERATURE RANGE ...

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... IDT82V3001A WAN PLL WITH SINGLE REFERENCE INPUT F8o C2o RSP TSP F8o MODE_sel0 MODE_sel1 TIE_en t RSPD t TSPW t TSPD Figure - 13 Output Timing Figure - 14 Input Control Setup and Hold Timing 26 INDUSTRIAL TEMPERATURE RANGE t RSPW ...

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... IDT82V3001A WAN PLL WITH SINGLE REFERENCE INPUT 7 ORDERING INFORMATION XXXXXXXX IDT Device Type DATASHEET DOCUMENT HISTORY 10/22/2003 pgs. 7, 23, 24. CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 XX X Process/ Package Temperature Range Blank PV 82V3001A for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com ...