AK4647VN AKM [Asahi Kasei Microsystems], AK4647VN Datasheet - Page 69

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AK4647VN

Manufacturer Part Number
AK4647VN
Description
Stereo CODEC with MIC/HP-AMP
Manufacturer
AKM [Asahi Kasei Microsystems]
Datasheet
ASAHI KASEI
Master clock can be stopped when ADC and DAC are not used.
MS0566-E-00
External LRCK
External MCKI
External BICK
1. PLL Master Mode
2. PLL Slave Mode (LRCK or BICK pin)
Stop of Clock
(Addr:01H, D0)
(Addr:01H, D1)
(Addr:01H, D0)
<Example>
<Example>
PMPLL bit
PMPLL bit
MCKO bit
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop MCKO clock: MCKO bit = “1” → “0”
(3) Stop an external master clock.
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop the external BICK and LRCK clocks
"1" or "0"
Input
Input
Input
(1)
(1)
(2)
(3)
(2)
(2)
Figure 54. Clock Stopping Sequence (1)
Figure 55. Clock Stopping Sequence (2)
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Example:
Example
Input Master Clock Select at PLL Mode: 11.2896MHz
BICK frequency at Master Mode: 64fs
Audio I/F Format : MSB justified (ADC & DAC)
Audio I/F Format: MSB justified (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
(1) (2) Addr:01H, Data:08H
(3) Stop an external MCKI
(2) Stop the external clocks
(1) Addr:01H, Data:00H
[AK4647]
2006/11

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