AK4647VN AKM [Asahi Kasei Microsystems], AK4647VN Datasheet - Page 42
AK4647VN
Manufacturer Part Number
AK4647VN
Description
Stereo CODEC with MIC/HP-AMP
Manufacturer
AKM [Asahi Kasei Microsystems]
Datasheet
1.AK4647VN.pdf
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ASAHI KASEI
When DACL bit is “1”, Lch/Rch signal of DAC is output from the LOUT/ROUT pins which is single-ended. When
DACL bit is “0”, output signal is muted and LOUT/ROUT pins output VCOM voltage. The load impedance is 10kΩ
(min.). When the PMLO bit = LOPS bit = “0”, the stereo line output enters power-down mode and the output is
pulled-down to AVSS by 100kΩ(typ). When the LOPS bit is “1”, stereo line output enters power-save mode. Pop noise at
power-up/down can be reduced by changing PMLO bit at LOPS bit = “1”. In this case, output signal line should be
pulled-down to AVSS by 20kΩ after AC coupled as Figure 31. Rise/Fall time is 300ms(max) at C=1μF. When PMLO bit
= “1”, LOPS bit = “0”, stereo line output is in normal operation.
LOVL bit set the gain of stereo line output.
MS0566-E-00
Stereo Line Output (LOUT/ROUT pins)
Figure 31. External Circuit for Stereo Line Output (in case of using Pop Reduction Circuit)
LOPS
0
1
Table 37. Stereo Line Output Mode Select (x: Don’t care)
LOVL
PMLO
0
1
0
1
0
1
DAC
Table 38. Stereo Line Output Volume Setting
Figure 30. Stereo Line Output
+2dB
Gain
0dB
Normal Operation
“DACL”
Power-down
Power-save
Power-save
ROUT
LOUT
Mode
- 42 -
Output Voltage (typ)
0.757 x AVDD
0.6 x AVDD
1μF
“LOVL”
220Ω
Pull-down to AVSS
Fall down to AVSS
Normal Operation
Rise up to VCOM
LOUT/ROUT pin
Default
20kΩ
ROUT pin
LOUT pin
Default
[AK4647]
2006/11
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