AK4647VN AKM [Asahi Kasei Microsystems], AK4647VN Datasheet - Page 47

• Manufacturer Part Number: AK4647VN
• Description: Stereo CODEC with MIC/HP-AMP
• Manufacturer: AKM [Asahi Kasei Microsystems]

ASAHI KASEI
(2) I
The AK4647 supports the fast-mode I
to (DVDD+0.3)V or less voltage.
(2)-1. WRITE Operations
Figure 36 shows the data transfer sequence for the I
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 42). After the
START condition, a slave address is sent. This address is 7 bits long followed by an eighth bit that is a data direction bit
(R/W). The most significant six bits of the slave address are fixed as “001001”. The next bit is CAD0 (device address bit).
This bit identifies the specific device on the bus. The hard-wired input pin (CAD0 pin) sets these device address bits
(Figure 37). If the slave address matches that of the AK4647, the AK4647 generates an acknowledge and the operation is
executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the
acknowledge clock pulse (Figure 43). A R/W bit value of “1” indicates that the read operation is to be executed. A “0”
indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK4647. The format is MSB first, and those most
significant 2-bits are fixed to zeros (Figure 38). The data after the second byte contains control data. The format is MSB
first, 8bits (Figure 39). The AK4647 generates an acknowledge after each byte has been received. A data transfer is
always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL
is HIGH defines a STOP condition (Figure 42).
The AK4647 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4647
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the
write cycle after the first data byte is transferred. After receiving each data packet the internal 6-bit address counter is
incremented by one, and the next data is automatically taken into the next address. If the address exceeds 24H prior to
generating a stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only change when the clock signal on the SCL line is LOW (Figure 44) except for the START and STOP
conditions.
MS0566-E-00
2
C-bus Control Mode (I2C pin = “H”)
SDA
S
T
A
R
T
S
Slave
Address
D7
0
0
R/W="0"
Figure 36. Data Transfer Sequence at the I
C
A
K
D6
0
0
Figure 39. Byte Structure after the second byte
Sub
Address(n)
(Those CAD0 should match with CAD0 pins)
2
C-bus (max: 400kHz). Pull-up resistors at SDA and SCL pins should be connected
D5
1
0
Figure 38. The Second Byte
Figure 37. The First Byte
A
C
K
2
C-bus mode. All commands are preceded by a START condition. A
Data(n)
A4
D4
0
- 47 -
C
A
K
A3
D3
0
Data(n+1)
2
A2
D2
C-Bus Mode
1
A
C
K
CAD0
A1
D1
C
A
K
Data(n+x)
R/W
A0
D0
A
C
K
S
T
O
P
P
[AK4647]
2006/11