AK4647VN AKM [Asahi Kasei Microsystems], AK4647VN Datasheet - Page 25

• Manufacturer Part Number: AK4647VN
• Description: Stereo CODEC with MIC/HP-AMP
• Manufacturer: AKM [Asahi Kasei Microsystems]

ASAHI KASEI
Upon power-up, the AK4647 should be reset by bringing the PDN pin = “L”. This ensures that all internal registers reset
to their initial values.
The ADC enters an initialization cycle that starts when the PMADL or PMADR bit is changed from “0” to “1” at PMDAC
bits is “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the ADC digital
data outputs of both channels are forced to a 2's compliment, “0”. The ADC output reflects the analog input signal after
the initialization cycle is complete. When PMDAC bit is “1”, the ADC does not require an initialization cycle.
The DAC enters an initialization cycle that starts when the PMDAC bit is changed from “0” to “1” at PMADL and
PMADR bits are “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the
DAC input digital data of both channels are internally forced to a 2's compliment, “0”. The DAC output reflects the digital
input data after the initialization cycle is complete. When PMADC or PMADR bit is “1”, the DAC does not require an
initialization cycle.
Three types of data formats are available and are selected by setting the DIF1-0 bits (seeTable 13). In all modes, the serial
data is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. LRCK
and BICK are output from the AK4647 in master mode, but must be input to the AK4647 in slave mode. The SDTO is
clocked out on the falling edge (“↓”) of BICK and the SDTI is latched on the rising edge (“↑”).
If 16-bit data that ADC outputs is converted to 8-bit data by removing LSB 8-bit, “−1” at 16bit data is converted to “−1”
at 8-bit data. And when the DAC playbacks this 8-bit data, “−1” at 8-bit data will be converted to “−256” at 16-bit data
and this is a large offset. This offset can be removed by adding the offset of “128” to 16-bit data before converting to 8-bit
data.
MS0566-E-00
System Reset
Audio Interface Format
Mode
0
1
2
3
LRCK
BICK(32fs)
SDTO(o)
BICK(64fs)
SDTO(o)
SDTI(i)
SDTI(i)
DIF1 bit
0
0
1
1
0
0 1
15 14
15 14
15 14 13
15:MSB, 0:LSB
1
DIF0 bit
2 3
2 3
Don't Care
13
13
0
1
0
1
Lch Data
7
7 6 5 4 3 2 1 0
1
Table 13. Audio Interface Format
15
I
SDTO (ADC)
MSB justified
MSB justified
9
2
S compatible
6 5 4 3
0
Figure 18. Mode 1 Timing
10
16
15 14
N/A
11 12 13 14 15 0 1 2 3
17 18
- 25 -
2
1 0
1 0
31 0 1 2 3
I
MSB justified
LSB justified
SDTI (DAC)
2
S compatible
15 14 13
15 14 13
15 14 13
N/A
Don't Care
Rch Data
7 6 5 4 3
7 6 5 4 3 2 1 0
1 0
≥ 32fs
≥ 32fs
≥ 32fs
BICK
15
9
N/A
10
16 17 18
15
11 12 13 14 15
14
Figure 18
Figure 19
Figure 20
Figure
-
2
2 1 0
1 0
31
Default
0
0
15
15
15
1
1
[AK4647]
2006/11