SCAN18373TSSC Fairchild Semiconductor, SCAN18373TSSC Datasheet
SCAN18373TSSC
Specifications of SCAN18373TSSC
Related parts for SCAN18373TSSC
SCAN18373TSSC Summary of contents
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... Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Device also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram © 2000 Fairchild Semiconductor Corporation Features IEEE 1149.1 (JTAG) Compliant Buffered active-low latch enable ...
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Functional Description The SCAN18373T consists of two sets of nine D-type latches with 3-STATE standard outputs. When the Latch Enable (ALE or BLE) input is HIGH, data on the inputs ( enters the latches. In this condition ...
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Block Diagrams (Continued) Note: BSR stands for Boundary Scan Register. Tap Controller Byte-B 3 www.fairchildsemi.com ...
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Description of Boundary-Scan Circuitry The scan cells used in the BOUNDARY-SCAN register are one of the following two types depending upon their loca- tion. Scan cell TYPE1 is intended to solely observe system data, while TYPE2 has the additional ability ...
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Description of Boundary-Scan Circuitry Scan Chain Definition (42 Bits in Length) (Continued) Boundary-Scan Register 5 www.fairchildsemi.com ...
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Description of Boundary-Scan Circuitry Boundary-Scan Register Definition Index Bit No. Pin Name 41 AOE 1 40 ACP 39 AOE 38 BOE 1 37 BCP 36 BOE ...
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Absolute Maximum Ratings Supply Voltage ( Input Diode Current ( 0. 0. Output Diode Current ( 0. 0. Output ...
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DC Electrical Characteristics Symbol Parameter I Maximum I per Input CCt CC Note 2: All outputs loaded; thresholds associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Noise Specifications Symbol Parameter ...
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AC Operating Requirements Normal Operation Symbol Parameter t Setup Time Data Hold Time Data t LE Pulse Width W Note 9: Voltage Range 5.0 is 5.0V 0.5V. ...
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AC Operating Requirements Scan Test Operation Symbol Parameter t Setup Time, S Data to TCK (Note 12) t Hold Time, H TCK to Data (Note 12) t Setup Time AOE , BOE to TCK (Note 13) ...
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Extended AC Electrical Characteristics Symbol Parameter t Propagation Delay PLH t Latch Enable to Output PHL t Propagation Delay PLH t Data to Output PHL t Output Enable Time PZH t PZL t Output Disable Time PHZ t PLZ t ...
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Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...