74LCX16841MTDX Fairchild Semiconductor, 74LCX16841MTDX Datasheet - Page 2

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74LCX16841MTDX

Manufacturer Part Number
74LCX16841MTDX
Description
IC LATCH TRANSP 20BIT LV 56TSSOP
Manufacturer
Fairchild Semiconductor
Series
74LCXr
Datasheet

Specifications of 74LCX16841MTDX

Logic Type
D-Type Transparent Latch
Circuit
10:10
Output Type
Tri-State
Voltage - Supply
2 V ~ 3.6 V
Independent Circuits
2
Delay Time - Propagation
1.5ns
Current - Output High, Low
24mA, 24mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
56-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74LCX16841MTDX
Manufacturer:
FAIRCHILD
Quantity:
607
Part Number:
74LCX16841MTDX
Manufacturer:
FAIRCHILD/仙童
Quantity:
20 000
www.fairchildsemi.com
Connection Diagram
Functional Description
The LCX16841 contains twenty D-type latches with
3-STATE standard outputs. The device is byte controlled
with each byte functioning identically, but independent of
the other. Control pins can be shorted together to obtain full
20-bit operation. The following description applies to each
byte. When the Latch Enable (LE
the D
transparent, i.e. a latch output will change states each time
Logic Diagrams
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
n
enters the latches. In this condition the latches are
n
) input is HIGH, data on
2
Truth Tables
H
L
X
Z
O
its D input changes. When LE
information that was present on the D inputs a setup time
preceding the HIGH-to-LOW transition of LE
3-STATE standard outputs are controlled by the Output
Enable (OE
puts are in the 2-state mode. When OE
dard outputs are in the high impedance mode but this does
not interfere with entering new data into the latches.
0
LOW Voltage Level
High Impedance
HIGH Voltage Level
Immaterial
Previous O
LE
LE
H
H
H
H
X
L
X
L
1
2
n
) input. When OE
0
before HIGH-to-LOW transition of Latch Enable
Inputs
Inputs
OE
OE
H
H
L
L
L
L
L
L
1
2
n
n
is LOW, the standard out-
D
is LOW, the latches store
D
10
0
X
H
X
X
H
X
–D
L
–D
L
9
19
n
is HIGH, the stan-
O
Outputs
Outputs
O
10
0
O
O
Z
H
Z
H
–O
L
–O
L
0
0
n
. The
9
19

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