74VHC573SJ Fairchild Semiconductor, 74VHC573SJ Datasheet
74VHC573SJ
Specifications of 74VHC573SJ
Related parts for 74VHC573SJ
74VHC573SJ Summary of contents
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... Pin and function compatible with 74HC573 Ordering Information Order Number Package Number 74VHC573M M20B 74VHC573SJ M20D 74VHC573MTC MTC20 Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering number. Pb-Free package per JEDEC J-STD-020B. Connection Diagram © ...
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... High Impedance Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1993 Fairchild Semiconductor Corporation 74VHC573 Rev. 1.3 Functional Description The VHC573 contains eight D-type latches with 3-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the D In this condition the latches are transparent, i ...
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... OPR Input Rise and Fall Time 3.3V ± 0. 5.0V ± 0.5V CC Note: 1. Unused inputs must be held HIGH or LOW. They may not float. ©1993 Fairchild Semiconductor Corporation 74VHC573 Rev. 1.3 Parameter (1) Parameter 3 Rating –0.5V to +7.0V –0.5V to +7.0V –0. 0.5V CC –20mA ±20mA ±25mA ± ...
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... OL (2) V Quiet Output Minimum OLV Dynamic V OL (2) V Minimum HIGH Level IHD Dynamic Input Voltage (2) V Maximum LOW Level ILD Dynamic Input Voltage Note: 2. Parameter guaranteed by design. ©1993 Fairchild Semiconductor Corporation 74VHC573 Rev. 1.3 T (V) Conditions Min. 1.50 0 –50µA 1 2.9 4 ...
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... CC IN calculated by the equation Operating Requirements Symbol Parameter t (H), t (L) Minimum Pulse Width (LE Minimum Setup Time S t Minimum Hold Time H ©1993 Fairchild Semiconductor Corporation 74VHC573 Rev. 1.3 V (V) Conditions CC 3.3 ± 0.3 C 15pF L C 50pF L 5.0 ± 0.5 C 15pF L C 50pF L 3.3 ± ...
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... Physical Dimensions Dimensions are in inches (millimeters) unless otherwise noted. Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide ©1993 Fairchild Semiconductor Corporation 74VHC573 Rev. 1.3 Package Number M20B 6 www.fairchildsemi.com ...
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... Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide ©1993 Fairchild Semiconductor Corporation 74VHC573 Rev. 1.3 Package Number M20D 7 www.fairchildsemi.com ...
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... Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 3. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide ©1993 Fairchild Semiconductor Corporation 74VHC573 Rev. 1.3 Package Number MTC20 8 www.fairchildsemi.com ...
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