74VHC373MX Fairchild Semiconductor, 74VHC373MX Datasheet - Page 2

• Manufacturer Part Number: 74VHC373MX
• Description: IC LATCH OCT D 3STATE 20SOIC
• Manufacturer: Fairchild Semiconductor
• Series: 74VHCr
• Type: D-Typer

Specifications of 74VHC373MX

• Logic Type: D-Type Transparent Latch
• Circuit: 8:8
• Output Type: Tri-State
• Voltage - Supply: 2 V ~ 5.5 V
• Independent Circuits: 1
• Delay Time - Propagation: 5ns
• Current - Output High, Low: 8mA, 8mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Logic Family: VHC
• Number Of Bits: 8
• Number Of Elements: 1
• Latch Mode: Transparent
• Polarity: Non-Inverting
• Technology: CMOS
• Package Type: SOIC W
• Propagation Delay Time: 17ns
• Operating Supply Voltage (typ): 2.5/3.3/5V
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Operating Supply Voltage (min): 2V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

©1993 Fairchild Semiconductor Corporation
74VHC373 Rev. 1.3
Logic Symbol
Truth Table
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O
Latch Enable
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
0
= Previous O
LE
H
H
X
L
Inputs
0
OE
before HIGH-to-LOW transition of
H
L
L
L
IEEE/IEC
D
X
H
X
L
n
Outputs
O
O
H
Z
L
n
0
Figure 1.
2
Functional Description
The VHC373 contains eight D-type latches with
3-STATE standard outputs. When the Latch Enable (LE)
input is HIGH, data on the D
In this condition the latches are transparent, i.e., a latch
output will change state each time its D input changes.
When LE is LOW, the latches store the information that
was present on the D inputs a setup time preceding the
HIGH-to-LOW transition of LE. The 3-STATE standard
outputs are controlled by the Output Enable (OE) input.
When OE is LOW, the standard outputs are in the
2-state mode. When OE is HIGH, the standard outputs
are in the high impedance mode but this does not inter-
fere with entering new data into the latches.
n
inputs enters the latches.
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