74LCX573MTC Fairchild Semiconductor, 74LCX573MTC Datasheet - Page 9

IC LATCH OCT D-TYPE 5V 20-TSSOP

74LCX573MTC

Manufacturer Part Number
74LCX573MTC
Description
IC LATCH OCT D-TYPE 5V 20-TSSOP
Manufacturer
Fairchild Semiconductor
Series
74LCXr
Type
D-Typer
Datasheet

Specifications of 74LCX573MTC

Logic Type
D-Type Transparent Latch
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
2 V ~ 3.6 V
Independent Circuits
1
Delay Time - Propagation
1.5ns
Current - Output High, Low
24mA, 24mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Logic Family
LCX
Number Of Bits
8
Number Of Elements
1
Latch Mode
Transparent
Polarity
Non-Inverting
Technology
CMOS
Package Type
TSSOP
Propagation Delay Time
10.5ns
Operating Supply Voltage (typ)
2.5/3.3V
High Level Output Current
-24mA
Low Level Output Current
24mA
Operating Supply Voltage (min)
2V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
20
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74LCX573MTC
Manufacturer:
ROHM
Quantity:
6 220
Part Number:
74LCX573MTCX
Manufacturer:
ST
0
Part Number:
74LCX573MTCX
Manufacturer:
FAIRCHILD/仙童
Quantity:
20 000
Part Number:
74LCX573MTCX-NL
Manufacturer:
LITELINK
Quantity:
4 613
©2006 Fairchild Semiconductor Corporation
74LCX573 Rev. 1.6.0
Physical Dimensions
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
10.65
10.00
INDICATOR
(R0.10)
PIN ONE
(R0.10)
7.60
7.40
B
Figure 3. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
2.65 MAX
1.27
0.40
(1.40)
20
1
SEATING PLANE
DETAIL A
0.75
0.25
SCALE: 2:1
0.35
0.51
0.25
13.00
12.60
11.43
X 45°
GAGE PLANE
0.25
M
C
B
A
1.27
0.30
0.10
11
10
NOTES: UNLESS OTHERWISE SPECIFIED
A
A) THIS PACKAGE CONFORMS TO JEDEC
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
D) CONFORMS TO ASME Y14.5M-1994
E) LANDPATTERN STANDARD: SOIC127P1030X265-20L
F) DRAWING FILENAME: MKT-M20BREV3
9
C
0.10 C
MS-013, VARIATION AC, ISSUE E
FLASH OR BURRS.
LAND PATTERN RECOMMENDATION
2.25
1.27
SEE DETAIL A
SEATING PLANE
0.65
www.fairchildsemi.com
0.33
0.20
9.50

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