COP87L84RK National Semiconductor, COP87L84RK Datasheet - Page 8

• Manufacturer Part Number: COP87L84RK
• Description: 8-Bit CMOS OTP Microcontrollers with 8k or 32k Memory/ Comparator/ and Single-slope A/D Capability
• Manufacturer: National Semiconductor

www.national.com
Instruction Cycle Time (t
Inputs
Output Propagation Delay (t
MICROWIRE
Input Pulse Width
Reset Pulse Width (Note 20)
Reference Voltage
V
Reference Supply
Current, I
DC Electrical Characteristics COP68xEB
Note 11: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at V
Note 12: The HALT mode will stop CKI from oscillating in the Crystal configurations. Halt test conditions: All inputs tied to V
figured as outputs and programmed low; D outputs programmed high. Parameter refers to HALT mode entered via setting bit 7 of the Port G data register. Part will
pull up CKI during HALT in crystal clock mode. Both CAN main comparator and the CAN Wakeup comparator need to be disabled.
Note 13: HALT and IDLE current specifications assume CAN block comparators are disabled.
Note 14: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages greater than V
to V
(typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 15: Condition and parameter valid only for part in HALT mode.
Note 16: Parameter characterized but not tested.
AC Electrical Characteristics COP68xEB and COP88xEB
t
Note 17: The maximum bus speed achievable with the CAN interface is a function of crystal frequency, message length and software overhead. The device can sup-
port a bus speed of up to 1 Mbit/S with a 10 MHz oscillator and 2 byte messages. The 1M bus speed refers to the rate at which protocol and data bits are transferred
on the bus. Longer messages require slower bus speeds due to the time required for software intervention between data bytes. The device will support a maximum
of 125k bits/s with eight byte messages and a 10 MHz oscillator.
Note 18: For device testing purpose of all AC parameters, V
Note 19: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 20: Parameter not tested.
On-Chip Voltage Reference
Note 21: Reference supply I
−55˚C
−55˚C
c
REF
Crystal/Resonator
t
t
SK, SO
All others
Setup Time (t
Hold Time (t
Output Pop Delay (t
Interrupt High Time
Interrupt Low Time
Timer 1, 2 High Time
Timer 1, 2 Low Time
SETUP
HOLD
= Instruction Cycle Time
CC
when biased at voltages greater than V
Parameter
DD
T
T
A
A
UWH
+125˚C
+125˚C
UWS
) (Note 20)
) (Note 20)
Parameter
UPD
DD
c
)
)
is supplied for information purposes only, it is not tested.
PD1
I
V
I
V
, t
OUT
OUT
CC
CC
PD0
= 5V
= 5V (Note 21)
= 0A, (No Load)
<
) (Note 19)
CC
80 µA,
(the pins do not have source current when biased at a voltage below V
Conditions
OH
will be tested at 0.5*V
V
V
V
C
V
V
CC
CC
CC
CC
CC
L
= 100 pF, R
4.5V
4.5V
4.5V
4.5V
4.5V
8
Conditions
CC
0.5V
(Continued)
.
L
CC
Min
= 2.2 k
−0.12
Min
200
1.0
1.0
60
20
56
1
1
1
1
CC
CC
0.5V
). The effective resistance to V
or GND, and outputs open.
CC
; Port C, G, E, F, L, M and N I/Os con-
Max
CC
CC
120
and the pins will have isnk current
Typ
+0.12
Max
220
DC
0.7
1
CC
Units
µA
V
is 750
Units
µs
ns
ns
µs
µs
ns
ns
ns
µs
t
t
t
t
c
c
c
c