COP87L84RK National Semiconductor, COP87L84RK Datasheet - Page 61

• Manufacturer Part Number: COP87L84RK
• Description: 8-Bit CMOS OTP Microcontrollers with 8k or 32k Memory/ Comparator/ and Single-slope A/D Capability
• Manufacturer: National Semiconductor

Baud Clock Generation
Note: The entries in Table 16 assume a prescaler output of 1.8432 MHz. In
As an example, considering the Asynchronous Mode and a
CKI clock of 4.608 MHz, the prescaler factor selected is:
4.608/1.8432 = 2.5
The 2.5 entry is available in Table 15 . The 1.8432 MHz pres-
caler output is then used with proper Baud Rate Divisor
( Table 1 ) to obtain different baud rates. For a baud rate of
19200 e.g., the entry in Table 16 is 5.
N − 1 = 5 (N − 1 is the value from Table 16 )
N = 6 (N is the Baud Rate Divisor)
Baud Rate = 1.8432 MHz/(16 x 6) = 19200
The divide by 16 is performed because in the asynchronous
mode, the input frequency to the USART is 16 times the
baud rate. The equation to calculate baud rates is given be-
low.
The actual Baud Rate may be found from:
BR = Fc/(16 X N X P)
Where:
BR is the Baud Rate
Fc is the CKI frequency
N is the Baud Rate Divisior ( Table 16 ).
P is the Prescaler Divide Factor selected by the value in the
Prescaler Select Register ( Table 15 )
Note: In the Synchronous Mode, the divisor 16 is replaced by two.
Example:
Asynchronous Mode:
Using the above equation N X P can be calculated first.
N x P = (5 X 10
Now 32.552 is divided by each Prescaler Factor ( Table 2 ) to
obtain a value closet to an integer. This factor happens to be
6.5 (P = 6.5).
N = 32.552/6.5 = 5.008 (N = 5)
The programmed value (from Table 10 ) should be 4 (N −1).
Using the above values calculated for N and P:
Crystal Frequency = 5 MHz
Desired baud rate = 9600
the asynchronous mode the baud rate could be as high as 625k.
134.5 (134.58)
110 (110.03)
TABLE 16. Baud Rate Divisors
(1.8432 MHz Prescaler Output)
19200
38400
Baud
1200
1800
2400
3600
4800
7200
9600
Rate
150
300
600
6
)/(16 x 9600) = 32.552
Divisor −1 (N-1)
Baud Rate
1046
855
767
383
191
95
63
47
31
23
15
11
(Continued)
5
2
61
BR = (5 x 10
% error = (9615.385 − 9600)/9600
Effect of HALT/IDLE
The USART logic is reinitialized when either the HALT or
IDLE modes are entered. This reinitialization sets the TBMT
flag and resets all read only bits in the USART control and
status registers. Read/Write bits remain unchanged. The
Transmit Buffer (TBUF) is not affected, but the Transmit Shift
register (TSFT) bits are set to one. The receiver registers
RBUF and RSFT are not affected.
The device will exit from the HALT/IDLE modes when the
Start bit of a character is detected at the RDX (L3) pin. This
feature is obtained by using the Multi-Input Wakeup scheme
provided on the device.
Before entering the HALT or IDLE modes the user program
must select the Wakeup source to be on the RXD pin. This
selection is done by setting bit 3 of WKEN (Wakeup Enable)
register. The Wakeup trigger condition is then selected to be
high to low transition. This is done via the WKEDG register.
(Bit 3 is one.)
If the device is halted and crystal oscillator is used, the
Wakeup signal will not start the chip running immediately be-
cause of the finite start up time requirement of the crystal os-
cillator. The idle timer (T0) generates a fixed (256 t
ensure that the oscillator has indeed stabilized before allow-
ing the device to execute code. The user has to consider this
delay when data transfer is expected immediately after exit-
ing the HALT mode.
Diagnostic
Bits CHL0 and CHL1 in the ENU register provide a loopback
feature for diagnostic testing of the USART. When these bits
are set to one, the following occur: The receiver input pin
(RDX) is internally connected to the transmitter output pin
(TDX); the output of the Transmitter Shift Register is “looped
back” into the Receive Shift Register input. In this mode,
data that is transmitted is immediately received. This feature
allows the processor to verify the transmit and receive data
paths of the USART.
Note that the framing format for this mode is the nine bit for-
mat; one Start bit, nine data bits, and 7/8, one or two Stop
bits. Parity is not generated or verified in this mode.
Attention Mode
The USART Receiver section supports an alternate mode of
operation, referred to as ATTENTION Mode. This mode of
operation is selected by the ATTN bit in the ENUR register.
The data format for transmission must also be selected as
having nine Data bits and either 7/8, one or two Stop bits.
The ATTENTION mode of operation is intended for use in
networking the device with other processors, Typically in
such environments the messages consists of device ad-
dresses, indicating which of several destinations should re-
ceive them, and the actual data. This Mode supports a
scheme in which addresses are flagged by having the ninth
bit of the data field set to a 1. If the ninth bit is reset to a zero
the byte is a Data byte.
While in ATTENTION mode, the USART monitors the com-
munication flow, but ignores all characters until an address
character is received. Upon receiving an address character,
the USART signals that the character is ready by setting the
RBFL flag, which in turn interrupts the processor if USART
Receiver interrupts are enabled. The ATTN bit is also cleared
6
)/(16 x 5 x 6.5) = 9615.384
*
100 = 0.16
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