COP87L84RK National Semiconductor, COP87L84RK Datasheet
COP87L84RK
Related parts for COP87L84RK
COP87L84RK Summary of contents
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... MICROWIRE ™ , MICROWIRE/PLUS ™ , and WATCHDOG TRI-STATE ® registered trademark of National Semiconductor Corporation. iceMASTER ® registered trademark of MetaLink Corporation. © 1999 National Semiconductor Corporation DS012837 Features include an 8-bit memory mapped architecture, 10 MHz CKI with 1µs instruction cycle, two multi-function 16-bit timer/counters, WATCHDOG 2 ...
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Basic Functional Description n CAN I/F — CAN serial bus interface block as described in the CAN specification part 2.0B (Passive) — Interface rates up to 250k bit/s are supported utilizing standard message identifiers n Programmable double buffered USART n ...
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Connection Diagrams Order Number COP888EB-XXX/V, COP688EB-XXX/V See NS Plastic Chip Package Number V44A Order Number COP889EB-XXX/V, COP689EB-XXX/V See NS Plastic Chip Package Number V68A Plastic Chip Carrier DS012837-2 Top View Plastic Leaded Chip Carrier Top View FIGURE 2. Connection Diagrams ...
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Connection Diagrams (Continued) Pinouts for 44-Pin and 68-Pin Packages Port ALT 44-Pin Type Pin Function PLCC G0 I/O INT G1 I/O WDOUT G2 I/O T1B G3 I/O T1A CKO ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Voltage at Any Pin −0. Electrical Characteristics COP88xEB −40˚C T +85˚C A Parameter Operating Voltage Power Supply Ripple (Note 2) ...
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DC Electrical Characteristics COP88xEB Note 3: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at V Note 4: The HALT mode will stop CKI from oscillating in the Crystal configurations. Halt ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Voltage at Any Pin −0. Electrical Characteristics COP68xEB −55˚C T +125˚C A Parameter Operating Voltage Power Supply Ripple (Note 10) ...
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DC Electrical Characteristics COP68xEB Note 11: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at V Note 12: The HALT mode will stop CKI from oscillating in the Crystal configurations. Halt ...
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CAN Comparator DC and AC Characteristics 4.8V V 5.2V, −40˚C T +125˚ Parameter Differential Input Voltage Input Offset Voltage 1.5V Input Common Mode Voltage Range Input Hysteresis A/D Converter Specifications (4.5V V 5.5V) (V − 0.050V) Any Input ...
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A/D Converter Specifications Typical Performance Characteristics www.national.com (Continued) DS012837-5 FIGURE 4. SPI Timing Diagram = +125˚C) (−55˚ DS012837-57 DS012837-59 10 DS012837-58 DS012837-60 ...
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Typical Performance Characteristics Pin Description V and GND are the power supply pins. CC CKI is the clock input. The clock can come from a crystal os- cillator (in conjunction with CKO). See Oscillator Description section. RESET is the master ...
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Pin Description (Continued) Writing a “1” to bit 6 of the Port G Configuration Register en- ables the MICROWIRE/PLUS to operate with the alternate phase of the SK clock Config. Reg. G7 CLKDLY G6 Alternate SK Port G has the ...
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Functional Description (Continued) CPU REGISTERS The CPU can do an 8-bit addition, subtraction, logical or shift operation in one instruction (t ) cycle time. c There are five CPU registers the 8-bit Accumulator Register PC is the 15-bit ...
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Functional Description The RESET signal goes directly to the HALT latch to restart a halted chip. When using external reset, the external RC network shown in Figure 6 should be used to ensure that the RESET pin is held low ...
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Control Registers (Continued) The ICNTRL register contains the following bits: Reserved This bit is reserved and should be zero LPEN L Port/M Port Interrupt Enable (Multi-Input Wakeup/Interrupt) T0PND Timer T0 Interrupt pending T0EN Timer T0 Interrupt Enable (Bit 12 toggle) ...
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Timers (Continued) TxB. The pin TxA supports I/O required by the timer block, while the pin TxB is an input to the timer block. The powerful and flexible timer block allows the device to easily perform all timer functions with ...
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Timers (Continued) sequently, the TxC0 control bit should be reset when enter- ing the Input Capture mode. The timer underflow interrupt is enabled with the TxENA control flag. When a TxA interrupt occurs in the Input Capture mode, the user ...
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Timers (Continued) The timer mode control bits (TxC3, TxC2 and TxC1) are detailed below: Mode TxC3 TxC2 Power Save Modes The ...
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Power Save Modes (Continued) 256 and is clocked with the t instruction cycle clock. The t c clock is derived by dividing the oscillator clock down by a fac- tor of 10. The Schmitt trigger following the CKI inverter on ...
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Multi-Input Wakeup (Continued) FIGURE 12. Port M Multi-Input Wake-up Logic This same procedure should be used following reset, since the Port L inputs are left floating as a result of reset. The oc- currence of the selected trigger condition for ...
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Multi-Input Wakeup (Continued) FIGURE 13. Port L Multi-Input Wake-Up Logic PORT M INTERRUPTS Port M provides the user with seven fully selectable, edge sensitive interrupts which are all vectored into the same ser- vice subroutine. The interrupt from Port M ...
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CAN Interface Block This device supports applications which require a low speed CAN interface designed to be programmed with two transmit and two receive registers. The user’s program may check the status bytes in order to get information ...
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Functional Block Description of the CAN Interface Interface Management Logic (IML) The IML executes the CPU’s transmission and reception commands and controls the data transfer between CPU, Rx/Tx and CAN registers. It provides the CAN Interface with Rx/Tx data from ...
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Functional Block Description of the CAN Interface In the case of an interrupt driven CAN interface, the calcula- tion of the actual t time would be done as follows: LOAD INT: ;Interrupt latency = 7tc = 7 µs PUSH A ...
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Functional Block Description of the CAN Interface (Continued) REGISTER DATA LENGTH CODE AND IDENTIFIERLOW REGISTER (RIDL)(Address X’00A6) RID3 RID2 RID1 RID0 RDLC3 RDLC2 Bit 7 This register is read only. RID3..RID0 Receive Identifier bits (lower four bits) The RID3..RID0 bits ...
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Functional Block Description of the CAN Interface (Continued) HALT mode (the CAN receive wakeup will still work) in order to reduce current consumption and to assure a proper resy- chronization to the bus after exiting the HALT mode. Note: A ...
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Functional Block Description of the CAN Interface (Continued) an interrupt by setting the Transmit Interrupt Enable bit (TIE). When servicing the interrupt the user has to make sure that TBE gets cleared by executing a WRITE instruction on the TxD2 ...
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... The following paragraphs provide a generic overview of the basic concepts of the Controller Area Network (CAN) as de- scribed in Chapter 4 of ISO/DIS11519-1. Implementation re- lated issues of the National Semiconductor device will be discussed as well. This device will process standard frame format only. Ex- tended frame formats will be acknowledged, however the data will be discarded ...
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Basic CAN Concepts (Continued) • Bus off A unit that is “bus off” has the output drivers disabled, i.e., it does not participate in any bus activity. Frame Formats INTRODUCTION There are basically two different types of frames used in ...
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Frame Formats (Continued) DATA FIELD The Data field consists of the data to be transferred within a data frame. It can contain bytes and each byte con- tains 8 bits. A remote frame has no data field. ...
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Frame Formats (Continued) An error frame can start anywhere in the middle of a frame. INT = Intermission Suspend Transmission is only for error passive nodes. An overload frame can only start at the end of a frame. ACK FIELD ...
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Frame Formats (Continued) ERROR FRAME The Error Frame consists of two bit fields: the error flag and the error delimiter. The error field is built up from the various error flags of the different nodes. Therefore, its length may vary ...
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Frame Formats (Continued) module 1 = error active transmitter detects bit error at t2 module 2 = error active receiver with a local fault at t1 module 3 = error active receiver detects stuff error at t2 FIGURE 24. Error ...
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Frame Formats (Continued) ORDER OF BIT TRANSMISSION A frame is transmitted starting with the Start of Frame, se- quentially followed by the remaining bit fields. In every bit field the MSB is transmitted first. FRAME VALIDATION Frames have a different ...
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Frame Formats (Continued) An error active unit can participate in bus communication and sends an active (“dominant”) error flag. • Error passive An error passive unit can participate in bus communication. However, if the unit detects an error it is ...
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Frame Formats (Continued) FIGURE 27. CAN Bus States SYNCHRONIZATION Every receiver starts with a “hard synchronization” on the falling edge of the SOF bit. One bit time consists of four bit segments: Synchronization segment, propagation segment, phase segment 1 and ...
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Frame Formats (Continued) Interrupts INTRODUCTION Each device supports fourteen vectored interrupts. Interrupt sources include Timer 0, Timer 1, Timer 2, Timer 3, Port L Wakeup, Software Trap, MICROWIRE/PLUS, and External Input. All interrupts force a branch to location 00FF Hex ...
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Interrupts (Continued) www.national.com FIGURE 31. Interrupt Block Diagram 38 DS012837-15 ...
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Interrupts (Continued) MASKABLE INTERRUPTS All interrupts other than the Software Trap are maskable. Each maskable interrupt has an associated enable bit and pending flag bit. The pending bit is set to 1 when the interrupt condition occurs. The state of ...
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Interrupts (Continued) ample, if the Software Trap routine is located at 0310 Hex, then the vector location 0yFE and -0yFF should contain the data 03 and 10 Hex, respectively. When a Software Trap in- terrupt occurs and the VIS instruction ...
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Interrupts (Continued) VIS Execution When the VIS instruction is executed it activates the arbitra- tion logic. The arbitration logic generates an even number between E0 and FE (E0, E2, E4, E6 etc...) depending on which active interrupt has the highest ...
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Interrupts (Continued) www.national.com DS012837-30 FIGURE 33. VIS Flowchart 42 ...
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Interrupts (Continued) Programming Example: External Interrupt PSW =00EF CNTRL =00EE RBIT 0,PORTGC RBIT 0,PORTGD SBIT IEDG, CNTRL SBIT EXEN, PSW SBIT GIE, PSW WAIT: JP WAIT . . . .=0FF VIS . . . .=01FA .ADDRW SERVICE . . INT_EXIT: ...
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Interrupts (Continued) NON-MASKABLE INTERRUPT Pending Flag There is a pending flag bit associated with the non-maskable interrupt, called STPND. This pending flag is not memory- mapped and cannot be accessed directly by the software. The pending flag is reset to ...
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... MICROWIRE/PLUS MICROWIRE/PLUS is a serial synchronous communications interface. The MICROWIRE/PLUS capability enables the de- vice to interface with any of National Semiconductor’s MI- CROWIRE peripherals (i.e., A/D converters, display drivers, E2PROMs etc.) and with other microcontrollers which sup- port the MICROWIRE interface. It consists of an 8-bit serial FIGURE 34 ...
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MICROWIRE/PLUS (Continued) MICROWIRE/PLUS Master Mode Operation In the MICROWIRE/PLUS Master mode of operation the shift clock (SK) is generated internally. The MICROWIRE Master always initiates all data exchanges. The MSEL bit in the CNTRL register must be set to enable ...
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Serial Peripheral Interface FIGURE 36. SPI Transmission Example The Serial Peripheral Interface (SPI) is used in master-slave bus systems synchronous bidirectional serial commu- nication interface with two data lines MISO and MOSI (Mas- ter In Slave Out, ...
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Serial Peripheral Interface The SPIU Control Register Bit 7 Bit 6 SRIE STIE SRIE SPI Receive Interrupt Enable 0 — disable receive interrupt 0 — enable receive interrupt B6 STIE SPI Transmit buffer Interrupt Enable 0 — ...
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Serial Peripheral Interface B[4:3] SPIMOD[1:0] SPI operation mode select SPIMOD[1: Slave mode, — SCK is SPI clock input — MISO is SPI data output — MOSI is SPI data input — slave select input 1 0: ...
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Serial Peripheral Interface SESSEN = 1, SCE = 0. If MOSI = 0 at the falling edge of SS, the ESS programming mode is detected and all N-port alternate functions are enabled. www.national.com (Continued) FIGURE 39. Programming the SPI Expander ...
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SPI Status Register a) Slave mode; rising SCK edge is active edge. (SPIMOD[1,0] = [0,0], SCE = 0) b) Slave mode; falling SCK edge is active edge. (SPIMOD[1,0] = [0,0], SCE = 1) FIGURE 41. Slave Mode Communication a) Master ...
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SPI Status Register (Continued) TABLE 14. SPI Status Register (SPISTAT) (0099) Bit 7 Bit 6 SRORN SRBNE 0 0 The SPI Status Register is a read only register. B7 SRORN SPI receiver overrun. This bit is set on the attempt ...
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SPI Status Register (Continued) SPI SYNCHRONIZATION After the SPI is enabled (SPIEN = 1), the SPI internal re- ceive and transmit shift clock is kept disabled until SS be- comes inactive. This includes SS being active at the time SPIEN ...
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A/D Converter (Continued) OPERATING MODES The A/D converter supports ratiometric measurements. It supports both Single Ended and Differential modes of opera- tion. Four specific analog channel selection modes are sup- ported. These are as follows: Allow any specific channel to ...
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A/D Converter (Continued) on for seven clock cycles. If the A single conversion mode, the conversion complete signal from the A/D will gen- erate a power down for the A/D converter and will clear the ADBSY bit in ...
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USART The device contains a full-duplex software programmable USART. The USART Figure 44 consists of a transmit shift register, a receiver shift register and seven addressable reg- isters, as follows: a transmit buffer register (TBUF), a re- ceiver buffer register ...
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USART (Continued) USART CONTROL AND STATUS REGISTERS The operation of the USART is programmed through three registers: ENU, ENUR and ENUI. DESCRIPTION OF USART REGISTER BITS ENU-USART Control and Status Register (Address at 0BA) PEN PSEL1 XBIT9/ CHL1 CHL0 ERR ...
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USART (Continued) ERI = 0 Interrupt from the receiver is disabled. ERI = 1 Interrupt from the receiver is enabled. ETI: This bit enables/disables interrupt from the transmitter section. Read/Write, cleared on reset. ETI = 0 Interrupt from the transmitter ...
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USART Operation (Continued) Note that the XBIT9/PSEL0 bit located in the ENU register serves two mutually exclusive functions. This bit programs the ninth bit for transmission when the USART is operating with nine data bits per frame. There is no ...
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Baud Clock Generation write registers shown in Figure 47 . Note that the 11-bit Baud Rate Divisor spills over into the Prescaler Select Register (PSR). PSR is cleared upon reset. As shown in Table Prescaler Factor of ...
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Baud Clock Generation (Continued) TABLE 16. Baud Rate Divisors (1.8432 MHz Prescaler Output) Baud Baud Rate Rate Divisor −1 (N-1) 110 (110.03) 1046 134.5 (134.58) 855 150 767 300 383 600 191 1200 95 1800 63 2400 47 3600 31 ...
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Attention Mode (Continued) automatically at this point, so that data characters as well as address characters are recognized. Software examines the contents of the RBUF and responds by deciding either to ac- cept the subsequent data stream (by leaving the ...
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WATCHDOG Operation (Continued) WATCHDOG AND CLOCK MONITOR SUMMARY The following salient points regarding the COP888 WATCH- DOG and CLOCK MONITOR should be noted: • Both the WATCHDOG and Clock Monitor detector cir- cuits are inhibited during RESET. • Following RESET, ...
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Memory Map All RAM, ports and registers (except A and PC) are mapped into data memory address space. Address Contents 0000 to 006F On-Chip RAM bytes (112 bytes) 0070 to 007F Unused RAM Address Space (Reads as All Ones) 0080 ...
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Memory Map (Continued) Address Contents 00CB A/D Converter Control Register (Reg:ENAD) 00CC A/D Converter Result Register (Reg:ADRSLT) 00CD to Reserved 00CE 00CF IDLE Timer Control Register (Reg:ITMR) 00D0 PORTLD, Port L Data Register 00D1 PORTLC, Port L Configuration Register 00D2 ...
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Addressing Modes (Continued) Absolute The mode is used with the JMP and JSR instructions, with the instruction field of 12 bits replacing the lower 12 bits of the program counter (PC). This allows jumping to any loca- tion in the ...
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Instruction Set (Continued) INSTRUCTION SET ADD A,Meml ADD ADC A,Meml ADD with Carry SUBC A,Meml Subtract with Carry AND A,Meml Logical AND ANDSZ A,Imm Logical AND Immed., Skip if Zero OR A,Meml Logical OR XOR A,Meml Logical EXclusive OR IFEQ ...
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Instruction Set (Continued) INSTRUCTION SET (Continued) JSRL Addr. Jump SubRoutine Long JSR Addr. Jump SubRoutine JID Jump InDirect RET RETurn from subroutine RETSK RETurn and SKip RETI RETurn from Interrupt INTR Generate an Interrupt NOP No OPeration www.national.com [SP] PL, ...
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Instruction Set (Continued) INSTRUCTION EXECUTION TIME Most instructions are single byte (with immediate addressing mode instructions taking two bytes). Most single byte instructions take one cycle time to execute. Skipped instructions require x number of cycles to be skipped, where ...
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Nibble Lower 70 ...
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Mask Options The COP684E and COP884EB mask programmable options are shown below. The options are programmed at the same time as the ROM pattern submission. OPTION 1: CLOCK CONFIGURATION = 1 Crystal Oscillator (CKI/10) G7 (CKO) is clock generator output ...
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Development Tools Support (Continued) COP8 Productivity Enhancement Tools • WCOP8 IDE: Very Low cost IDE (Integrated Develop- ment Environment) from KKD. Supports COP8C, COP8- NSASM, COP8-MLSIM, DriveWay COP8, and MetaLink debugger under a common Windows Project Manage- ment environment. Code ...
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Development Tools Support OTP Programmers Contact vendors < Cost: Free $100 $100 - $300 $300 - $1k $1k - $3k $3k - $5k WHERE TO GET TOOLS Tools are ordered ...
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Physical Dimensions inches (millimeters) unless otherwise noted Order Number COP888EB-XXX/V, COP688EB-XXX/V Order Number COP889EB-XXX/V, COP689EB-XXX/V www.national.com 44-Lead Molded Plastic Leaded Chip Carrier NS Plastic Chip Package Number V44A 68-Lead Molded Plastic Leaded Chip Carrier NS Plastic Chip Package Number V68A ...
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... NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant ...