COP87L84RK National Semiconductor, COP87L84RK Datasheet - Page 18

• Manufacturer Part Number: COP87L84RK
• Description: 8-Bit CMOS OTP Microcontrollers with 8k or 32k Memory/ Comparator/ and Single-slope A/D Capability
• Manufacturer: National Semiconductor

www.national.com
Timers
The timer mode control bits (TxC3, TxC2 and TxC1) are detailed below:
Mode
Power Save Modes
The device offer the user two power save modes of opera-
tion: HALT and IDLE. In the HALT mode, all microcontroller
activities are stopped. In the IDLE mode, the on-board oscil-
lator circuitry and timer T0 are active but all other microcon-
troller activities are stopped. In either mode, all on-board
RAM, registers, I/O states, and timers (with the exception of
T0) are unaltered.
HALT MODE
The device is placed in the HALT mode by writing a ’’1” to the
HALT flag (G7 data bit). All microcontroller activities, includ-
ing the clock, and timers, are stopped. In the HALT mode,
the power requirements of the device are minimal and the
applied voltage (V
without altering the state of the machine.
The following table shows the two CAN power save modes and the active CAN transceiver blocks:
The device supports two different ways of exiting the HALT
mode. The first method of exiting the HALT mode is with the
Multi-Input Wakeup feature on the L & M port. The second
method of exiting the HALT mode is by pulling the RESET
pin low.
Since a crystal or ceramic resonator may be selected as the
oscillator, the Wakeup signal is not allowed to start the chip
1
2
3
Step 1
0
0
1
1
(Continued)
TxC3
1
1
0
0
0
1
0
1
CC
) may be decreased to Vr (Vr = 2.0V)
Step 2
0
1
0
1
TxC2
0
0
0
0
1
1
1
1
TxC1
1
0
0
1
0
0
1
1
Main-Comp
on
on
off
off
PWM: TxA Toggle
PWM: No TxA
Toggle
External Event
Counter
External Event
Counter
Captures:
TxA Pos. Edge
TxB Pos. Edge
Captures:
TxA Pos. Edge
TxB Neg. Edge
Captures:
TxA Neg. Edge
TxB Neg. Edge
Captures:
TxA Neg. Edge
TxB Neg. Edge
Description
18
Wake-Up-Comp
CAN HALT/IDLE mode:
In order to reduce the device overall current consumption in
HALT/IDLE mode a two step power save mechanism is
implemented on the device:
Step 1:
Step 2:
Note: If both the main receive comparator and the wake-up comparator are
running immediately since crystal oscillators and ceramic
resonators have a delayed start up time to reach full ampli-
tude and frequency stability. The IDLE timer is used to gen-
erate a fixed delay to ensure that the oscillator has indeed
stabilized before allowing instruction execution. In this case,
upon detecting a valid Wakeup signal, only the oscillator cir-
cuitry is enabled. The IDLE timer is loaded with a value of
on
off
on
off
disabled the on chip CAN voltage reference is also disabled. The CAN-
V
REF
Autoreload RA
Autoreload RA
Timer
Underflow
Timer
Underflow
Pos. TxA Edge
or Timer
Underflow
Pos. TxA
Edge or Timer
Underflow
Neg. TxA
Edge or Timer
Underflow
Neg. TxA
Edge or Timer
Underflow
output is then High-Z
Disable main receive comparator. This is done by
resetting both the TxEN0 and TxEN1 bits in the
CBUS register. Note: These bits should always be
reset before entering HALT/IDLE mode to allow
proper resynchronization to the CAN bus after ex-
iting HALT/IDLE mode.
Disable the CAN wake-up comparators, this is
done by resetting bit 7 in the port-m wakeup en-
able register (MWKEN) a transition on the CAN
bus will then not wake the device up.
Interrupt A
Source
CAN-V
Autoreload RB
Autoreload RB
Pos. TxB Edge
Pos. TxB Edge
Pos. TxB Edge
Neg. TxB
Edge
Neg. TxB
Edge
Neg. TxB
Edge
on
on
on
off
Interrupt B
REF
Source
V
t
t
Pos. TxA
Edge
Pos. TxA
Edge
t
t
t
t
C
C
C
C
C
C
Counts On
High-Z
REF
V
V
V
CC
CC
CC
Timer
Pin
/2
/2
/2