ST92T163 ST Microelectronics, ST92T163 Datasheet - Page 53

• Manufacturer Part Number: ST92T163
• Description: 8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS
• Manufacturer: ST Microelectronics

ARBITRATION MODES (Cont’d)
End of Interrupt Routine
The iret Interrupt Return instruction executes
the following steps:
– The Flag register is popped from system stack.
– If ENCSR is set, CSR is popped from system
– The PC high byte is popped from system stack.
– The PC low byte is popped from system stack.
– All unmasked Interrupts are enabled by setting
– The priority level of the interrupted routine is
Figure 25. Complex Example of a Sequence of Interrupt Requests with:
- Nested mode
- IEN set to 1 during the interrupt routine execution
Priority Level of
Interrupt Request
0
1
2
3
4
5
6
7
stack.
the CICR.IEN bit.
popped from the special register (NICR) and
copied into CPL.
CPL is set to 7
INT5
MAIN
ei
CPL=5
INT 5
INT2
INT3
INT4
ei
CPL=2
INT0
INT 2
ei
CPL2 < CPL4:
Serviced just after ei
CPL=0
INT 0
CPL=2
INT 2
ei
CPL6 > CPL3:
INT6 pending
CPL=3
INT 3
INT6
CPL=4
INT 4
INT2
ei
– If ENCSR is reset, CSR is used instead of ISR,
The suspended routine thus resumes at the inter-
rupted instruction.
Figure 24 contains a simple example, showing that
if the ei instruction is not used in the interrupt
service routines, nested and concurrent modes
are equivalent.
Figure 25 contains a more complex example
showing how nested mode allows nested interrupt
processing (enabled inside the interrupt service
routines using the ei instruction) according to
their priority level.
CPL=2
INT 2
unless the program returns to another nested
routine.
CPL=4
INT 4
CPL=5
INT 5
INTERRUPT 0 HAS PRIORI TY LEVEL 0
INTERRUPT 2 HAS PRIORI TY LEVEL 2
INTERRUPT 3 HAS PRIORI TY LEVEL 3
INTERRUPT 4 HAS PRIORI TY LEVEL 4
INTERRUPT 5 HAS PRIORI TY LEVEL 5
INTERRUPT 6 HAS PRIORI TY LEVEL 6
ST92163 - INTERRUPTS
CPL=6
INT 6
MAIN
CPL=7
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