ST92T163 ST Microelectronics, ST92T163 Datasheet - Page 144

• Manufacturer Part Number: ST92T163
• Description: 8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS
• Manufacturer: ST Microelectronics

ST92163 - USB PERIPHERAL (USB)
USB INTERFACE (Cont’d)
Bit 5:4 = STAT_TX [1:0] Status bits, for transmis-
sion transfers .
These bits contain the information about the end-
point status, which are listed below:
Table 25. Transmission status encoding
These bits are written by software, but hardware
sets the STAT_TX bits to NAK when a correct
transfer has occurred (CTR=1) related to a IN or
SETUP (control only) transaction addressed to
this endpoint, waiting for the software to prepare
the next set of data to be transmitted. If the end-
point is defined as isochronous, its status can be
only “VALID” or “DISABLED” so no hardware
change of the endpoint status will take place after
a successful transaction.
Bits 3:2 = PIDR[1:0]: PID Received .
These bits are read-only and contain the two most
significant bits of the PID field of the last token PID
addressed to this endpoint.
These bits are kept frozen while CTR bit is at 1.
The USB standard defines PIDR bits as in the fol-
lowing table:
Table 26. PID encoding
Bit 1 = CEP: Control Endpoint .
Software must set this bit to configure this end-
point as a control endpoint.
0: Non-control endpoint
1: Control endpoint
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STAT_TX
[1:0]
00
01
10
11
PIDR[1:0]
00
10
11
DISABLED: all transmission requests ad-
dressed to this endpoint are ignored.
STALL: the endpoint is stalled and all trans-
mission requests result in a STALL hand-
shake.
NAK: the endpoint is NAKed and all trans-
mission requests result in a NAK hand-
shake.
VALID: this endpoint is enabled for trans-
mission.
OUT
IN
SETUP
Meaning
PID
Notes: If a control endpoint is defined as NAK in
the receive direction, the USB interface will not an-
swer, when a SETUP transaction is received.
If the control endpoint is defined as STALL in the
receive direction, then the SETUP packet will be
accepted anyway, transferring data and issuing
the CTR interrupt.
Bit 0 = ISO: Isochronous endpoint .
Software must set this bit to configure this end-
point as an isochronous endpoint.
0: Not an isochronous endpoint
1:isochronous endpoint
Note: Since isochronous transfer has no hand-
shake phase, the only legal values for the
STAT_RX/STAT_TX bit pairs are ‘00’ (Disabled)
and ‘11’ (Valid), any other value will produce re-
sults not compliant to the USB standard. Iso-
chronous endpoints implement double-buffering,
using both ‘transmission’ and ‘reception’ memory
areas to manage buffer swapping on each suc-
cessful transaction.
The memory buffer that is currently used by the
USB interface is defined by the DTOG bit corre-
sponding to the endpoint direction (DTOG_RX in
EPnRB for ‘reception’ isochronous endpoints,
DTOG_TX in EPnRA for ‘transmission’ iso-
chronous endpoints) according to the following ta-
ble:
Table 27. Isochronous memory buffers usage
Since the swapped buffer management requires
the usage of all 8 Register File locations hosting
the address pointer and the length of the allocated
memory buffers, isochronous endpoints are forced
to be unidirectional so it is not possible to enable
an isochronous endpoint both for transmission and
reception.
DTOG bit
value
0
1
DMA buffer used by
ADDRn_T /
COUNTn_T register
file locations.
ADDRn_R /
COUNTn_R register
file locations.
USB Interface
DMA buffer used by
ADDRn_R /
COUNTn_R register
file locations.
ADDRn_T /
COUNTn_T register
file locations.
application
software