ST92T163 ST Microelectronics, ST92T163 Datasheet - Page 128

• Manufacturer Part Number: ST92T163
• Description: 8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS
• Manufacturer: ST Microelectronics

ST92163 - MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
EXTERNAL
(T_ICR)
R250 - Read/Write
Register Page: 10
Reset value: 0000 0000 (00h)
Bit 7:4 = IN[3:0]: Input pin function.
These bits are set and cleared by software.
Bit 3:2 = A[0:1]: TxINA Pin event .
These bits are set and cleared by software.
128/224
IN3
7
IN[3:0] bits
A0
0
0
1
1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
IN2
IN1
A1
INPUT
0
1
0
1
Pin Function
Trigger Up
Autodiscr.
Ext. Clock
IN0
Clock Up
Up/Down
Up/Down
not used
not used
not used
Trigger
Trigger
Trigger
Trigger
No operation
Falling edge sensitive
Rising edge sensitive
Rising and falling edges
TxINA
Gate
Gate
Gate
CONTROL
A0
TxINA Pin Event
A1
Pin Function
Trigger Down
TxINB Input
Clock Down
Ext. Clock
Ext. Clock
Ext. Clock
Ext. Clock
Autodiscr.
not used
not used
not used
not used
REGISTER
Trigger
Trigger
Trigger
Trigger
Gate
B0
B1
0
Bit 1:0 = B[0:1]: TxINB Pin event .
These bits are set and cleared by software.
PRESCALER REGISTER (PRSR)
R251 - Read/Write
Register Page: 10
Reset value: 0000 0000 (00h)
This register holds the preset value for the 8-bit
prescaler. The PRSR content may be modified at
any time, but it will be loaded into the prescaler at
the following prescaler underflow, or as a conse-
quence of a counter reload (either by software or
upon external request).
Following a RESET condition, the prescaler is au-
tomatically loaded with 00h, so that the prescaler
divides by 1 and the maximum counter clock is
generated (OSCIN frequency divided by 6 when
MODER.5 = DIV2 bit is set).
The binary value programmed in the PRSR regis-
ter is equal to the divider value minus one. For ex-
ample, loading PRSR with 24 causes the prescal-
er to divide by 25.
P7
7
B0
0
0
1
1
P6
B1
P5
0
1
0
1
P4
No operation
Falling edge sensitive
Rising edge sensitive
Rising and falling edges
P3
TxINB Pin Event
P2
P1
P0
0