ATTIny2313-16MI ATMEL Corporation, ATTIny2313-16MI Datasheet - Page 147
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ATTIny2313-16MI
Manufacturer Part Number
ATTIny2313-16MI
Description
8-bit AVR Microcontroller with 2K Bytes In-System Programmable Flash
Manufacturer
ATMEL Corporation
Datasheet
1.ATTINY2313-16MI.pdf
(211 pages)
- Current page: 147 of 211
- Download datasheet (3Mb)
USI Control Register – USICR
2543C–AVR–12/03
Note that even when no wire mode is selected (USIWM1..0 = 0) the external clock input
(USCK/SCL) are can still be used by the counter.
The Control Register includes interrupt enable control, wire mode setting, Clock Select
setting, and clock strobe.
• Bit 7 – USISIE: Start Condition Interrupt Enable
Setting this bit to one enables the Start Condition detector interrupt. If there is a pending
interrupt when the USISIE and the Global Interrupt Enable Flag is set to one, this will
immediately be executed.
• Bit 6 – USIOIE: Counter Overflow Interrupt Enable
Setting this bit to one enables the Counter Overflow interrupt. If there is a pending inter-
rupt when the USIOIE and the Global Interrupt Enable Flag is set to one, this will
immediately be executed.
• Bit 5..4 – USIWM1..0: Wire Mode
These bits set the type of wire mode to be used. Basically only the function of the
outputs are affected by these bits. Data and clock inputs are not affected by the mode
selected and will always have the same function. The counter and Shift Register can
therefore be clocked externally, and data input sampled, even when outputs are
disabled. The relations between USIWM1..0 and the USI operation is summarized in
Table 61 on page 148.
Bit
Read/Write
Initial Value
USISIE
R/W
7
0
USIOIE
R/W
6
0
USIWM1
R/W
5
0
USIWM0
R/W
4
0
USICS1
R/W
3
0
USICS0
R/W
2
0
ATtiny2313/V
USICLK
W
1
0
USITC
W
0
0
USICR
147
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