ATTIny2313-16MI ATMEL Corporation, ATTIny2313-16MI Datasheet - Page 111

• Manufacturer Part Number: ATTIny2313-16MI
• Description: 8-bit AVR Microcontroller with 2K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

Timer/Counter Interrupt Flag
Register – TIFR
2543C–AVR–12/03
• Bit 3 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The
corresponding Interrupt Vector (See “Interrupts” on page 44.) is executed when the
ICF1 flag, located in TIFR, is set.
• Bit 7 – TOV1: Timer/Counter1, Overflow Flag
The setting of this flag is dependent of the WGM13:0 bits setting. In Normal and CTC
modes, the TOV1 flag is set when the timer overflows. Refer to Table 47 on page 107
for the TOV1 flag behavior when using another WGM13:0 bit setting.
TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is
executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location.
• Bit 6 – OCF1A: Timer/Counter1, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Out-
put Compare Register A (OCR1A).
Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A flag.
OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is
executed. Alternatively, OCF1A can be cleared by writing a logic one to its bit location.
• Bit 5 – OCF1B: Timer/Counter1, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Out-
put Compare Register B (OCR1B).
Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B flag.
OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is
executed. Alternatively, OCF1B can be cleared by writing a logic one to its bit location.
• Bit 3 – ICF1: Timer/Counter1, Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture
Register (ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 flag is set
when the counter reaches the TOP value.
ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alter-
natively, ICF1 can be cleared by writing a logic one to its bit location.
Bit
Read/Write
Initial Value
TOV1
R/W
7
0
OCF1A
R/W
6
0
OCF1B
R/W
5
0
R
4
–
0
ICF1
R/W
3
0
OCF0B
R/W
2
0
ATtiny2313/V
TOV0
R/W
1
0
OCF0A
R/W
0
0
TIFR
111