DSM2150F5V STMicroelectronics, DSM2150F5V Datasheet - Page 71

• Manufacturer Part Number: DSM2150F5V
• Description: DSM (Digital Signal Processor System Memory) for Analog Devices DSPs (3.3V Supply)
• Manufacturer: STMicroelectronics

Table 48. Page Register
Note: Bit Definitions:
Table 49. PMMR0 Register
Note: The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET) pulses do not clear the registers.
Note: Bit Definitions:
Table 50. PMMR2 Register
Note: For Bit 4, Bit 3, Bit 2: See Table
Note: Bit Definitions:
Table 51. Memory_ID0 Register
Note: Bit Definitions:
Table 52. Memory_ID1 Register
Note: Bit Definitions:
Bit 7
PGR 7
Bit 7
not used
(set to 0)
Bit 7
not used
(set to 0)
Bit 7
not used
(set to 0)
Bit 7
not used
(set to 0)
Configure Page input to PLD. Default is PGR7-PGR0=0.
PLD Turbo
PLD Array CLK
PLD MCells CLK 0 = CLKIN to the PLD Macrocells is connected.
PLD Array Addr
PLD Array CNTL2 0 = CNTL2 input to the PLD AND array is connected. Every CLKIN change powers up the PLD when Turbo bit is off.
PLD Array CNTL1 0 = CNTL1 input to the PLD AND array is connected. Every CLKIN change powers up the PLD when Turbo bit is off.
PLD Array CNTL0 0 = CNTL0 input to the PLD AND array is connected. Every CLKIN change powers up the PLD when Turbo bit is off.
PLD Array WRH 0 = WRH input to the PLD AND array is connected.
F_size[3:0]
B_size[3:0]
6h = Primary Flash memory size is 8Mbit
3h = Secondary NVM size is 512Kbit
Bit 6
PGR 6
Bit 6
not used
(set to 0)
Bit 6
PLD
Array WRH
Bit 6
not used
(set to 0)
Bit 6
not used
(set to 0)
0 = PLD Turbo is on.
1 = PLD Turbo is off, saving power.
0 = CLKIN to the PLD AND array is connected. Every CLKIN change powers up the PLD when Turbo bit is off.
1 = CLKIN to the PLD AND array is disconnected, saving power.
1 = CLKIN to the PLD Macrocells is disconnected, saving power.
0 = Address A7-A0 are connected to the PLD array.
1 = Address A7-A0 are blocked from the PLD array, saving power.
1 = CNTL2 input to the PLD AND array is disconnected, saving power.
1 = CNTL1 input to the PLD AND array is disconnected, saving power.
1 = CNTL0 input to the PLD AND array is disconnected, saving power.
1 = WRH input to the PLD AND array is disconnected, saving power.
5h = Primary Flash memory size is 4Mbit
2h = Secondary NVM size is 256Kbit
Bit 5
PGR 5
Bit 5
PLD
MCells CLK
Bit 5
not used
(set to 0)
Bit 5
not used
(set to 0)
Bit 5
not used
(set to 0)
49
for the signals that are blocked on pins CNTL0-CNTL2.
Bit 4
PGR 4
Bit 4
PLD
Array CLK
Bit 4
PLD Array
CNTL2
Bit 4
not used
(set to 0)
Bit 4
not used
(set to 0)
Bit 3
PGR 3
Bit 3
PLD
Turbo
Bit 3
PLD Array
CNTL1
Bit 3
F_size 3
Bit 3
B_size 3
Bit 2
PGR 2
Bit 2
not used
(set to 0)
Bit 2
PLD Array
CNTL0
Bit 2
F_size 2
Bit 2
B_size 2
Bit 1
PGR 1
Bit 1
not used
(set to 0)
Bit 1
not used
(set to 0)
Bit 1
F_size 1
Bit 1
B_size 1
DSM2150F5V
Bit 0
PGR 0
Bit 0
not used
(set to 0)
Bit 0
PLD
Array Addr
Bit 0
F_size 0
Bit 0
B_size 0
71/73