DSM2150F5V STMicroelectronics, DSM2150F5V Datasheet - Page 47

• Manufacturer Part Number: DSM2150F5V
• Description: DSM (Digital Signal Processor System Memory) for Analog Devices DSPs (3.3V Supply)
• Manufacturer: STMicroelectronics

POWER MANAGEMENT
The device offers configurable power saving op-
tions. These options may be used individually or in
combinations, as follows:
–
–
All memory blocks in the device are built with
zero-power technology. Zero-power
technology puts the memories into Standby
Mode when address/data inputs are not
changing (zero DC current). As soon as a
transition occurs on an address input, the
affected memory “wakes up”, changes and
latches its outputs, then goes back to standby.
The designer does not have to do anything
special to achieve memory Standby Mode
when no inputs are changing—it happens
automatically.
Both PLDs (DPLD and CPLD) are also Zero-
power, but this is not the default operation.
The DSP must set a bit at run-time to achieve
Zero-power as described.
PSD Chip Select Input (CSI, PD2) can be
used to disable the internal memories and
csiop registers, placing them in Standby Mode
even if address inputs are changing. This
feature does not block any internal signals or
disable the PLDs. There is a slight penalty in
memory access time when PSD Chip Select
Input (CSI, PD2) makes its initial transition
from deselected to selected.
–
–
The PMMR registers can be written by the
DSP at run-time to manage power. The device
has a Turbo Bit in the PMMR0 register. This bit
can be set to turn the Turbo Mode off (the
default is with Turbo Mode turned on). While
Turbo Mode is off, the PLDs can achieve
standby current when no PLD inputs are
changing (zero DC current). Even when inputs
do change, significant power can be saved at
lower frequencies (AC current), compared to
when Turbo Mode is on. When the Turbo
Mode is on, there is a significant DC current
component and the AC component is higher.
Further significant power savings can be
achieved by blocking signals that are not used
in DPLD or CPLD logic equations. The
“blocking bits” in PMMR registers can be set to
logic ’1’ by the DSP to block designated
signals from reaching both PLDs. Current
consumption of the PLDs is directly related to
the composite frequency of the changes on
their inputs (see
blocking unused PLD inputs can significantly
lower PLD operating frequency and power
consumption. The DSP also has the option of
blocking certain PLD inputs when not needed,
then letting them pass for when needed for
specific logic operations.
and Appendix A define the PMMR registers.
Figure 23., page
Table 4., page 13
DSM2150F5V
51), so
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