DSM2150F5V STMicroelectronics, DSM2150F5V Datasheet - Page 31

• Manufacturer Part Number: DSM2150F5V
• Description: DSM (Digital Signal Processor System Memory) for Analog Devices DSPs (3.3V Supply)
• Manufacturer: STMicroelectronics

The OMC Mask Register
There is one Mask Register for each of the two
groups of eight OMCs. The Mask Registers can be
used to block the loading of data to individual
OMCs. The default value for the Mask Registers is
00h, which allows loading of all the OMCs. When
a given bit in a Mask Register is set to a ’1,’ the
DSP is blocked from writing to the associated
OMC. For example, suppose McellA0-3 are being
used for a state machine. You would not want a
DSP WRITE to McellA to overwrite the state ma-
chine registers. Therefore, you would want to load
the Mask Register for McellA group with the value
0Fh.
The Output Enable of the OMC
The OMC block can be connected to an I/O port
pin as a PLD output. The output enable of each
port pin driver is controlled by a single product
term from the AND Array, ORed with the Direction
Register output. The pin is enabled upon Power-
up if no output enable equation is defined and if
the pin is declared as a PLD output in PSDsoft Ex-
press.
If the OMC output is specified as an internal node
and not as a port pin output in the PSDsoft Ex-
press, then the port pin can be used for other I/O
functions. The internal node feedback can be rout-
ed as an input to the AND Array.
Input Macrocells (IMC)
The CPLD has 24 IMCs, one for each pin on Ports
A, B and C. The architecture of the IMCs is shown
in
configurable, and can be used as a latch, a regis-
ter, or to pass incoming Port signals prior to driving
them onto the PLD input bus. This is useful for
sampling and debouncing inputs to the AND array
(keypad inputs, etc.). Additionally, the outputs of
the IMCs can be read by the DSP asynchronously
at any time through the internal data bus using the
csiop register block (see
The enable for the latch and clock for the register
are driven by a product term from the CPLD. Each
product term output is used to latch or clock four
IMCs. Port inputs 3-0 can be controlled by one
product term and 7-4 by another.
Configurations for the IMCs are specified by equa-
tions specified in PSDsoft Express. See Applica-
tion Note AN1171.
Figure 10., page
32. The IMCs are individually
Table 4., page
DSM2150F5V
13).
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