LH28F800 Sharp Electrionic Components, LH28F800 Datasheet - Page 34
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LH28F800
Manufacturer Part Number
LH28F800
Description
8 M-bit (512 kB x 16) SmartVoltage Flash Memories
Manufacturer
Sharp Electrionic Components
Datasheet
1.LH28F800.pdf
(45 pages)
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6.2.5 AC CHARACTERISTICS FOR WE#-CONTROLLED WRITE OPERATIONS
NOTES :
1. Read timing characteristics during block erase, word
2. Sampled, not 100% tested.
SYMBOL
SYMBOL
•
• V
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AVAV
PHWL
ELWL
WLWH
PHHWH
VPWH
AVWH
DVWH
WHDX
WHAX
WHEH
WHWL
WHRL
WHGL
QVVL
QVPH
AVAV
PHWL
ELWL
WLWH
PHHWH
VPWH
AVWH
DVWH
WHDX
WHAX
WHEH
WHWL
WHRL
WHGL
QVVL
QVPH
V
CC
CC
write and lock-bit configuration operations are the same
as during read-only operations. Refer to Section 6.2.4
"AC CHARACTERISTICS" for read-only operations.
= 2.7 to 3.0 V, T
= 3.3±0.3 V, T
Write Cycle Time
RP# High Recovery to WE# Going Low
CE# Setup to WE# Going Low
WE# Pulse Width
RP# V
V
Address Setup to WE# Going High
Data Setup to WE# Going High
Data Hold from WE# High
Address Hold from WE# High
CE# Hold from WE# High
WE# Pulse Width High
WE# High to RY/BY# Going Low
Write Recovery before Read
V
RP# V
Write Cycle Time
RP# High Recovery to WE# Going Low
CE# Setup to WE# Going Low
WE# Pulse Width
RP# V
V
Address Setup to WE# Going High
Data Setup to WE# Going High
Data Hold from WE# High
Address Hold from WE# High
CE# Hold from WE# High
WE# Pulse Width High
WE# High to RY/BY# Going Low
Write Recovery before Read
V
RP# V
PP
PP
PP
PP
Setup to WE# Going High
Hold from Valid SRD, RY/BY# High
Setup to WE# Going High
Hold from Valid SRD, RY/BY# High
HH
HH
HH
HH
Setup to WE# Going High
Hold from Valid SRD, RY/BY# High
Setup to WE# Going High
Hold from Valid SRD, RY/BY# High
A
= 0 to +70˚C or –40 to +85
A
PARAMETER
PARAMETER
= 0 to +70
VERSIONS
VERSIONS
˚
C or –40 to +85
˚
C
˚
C
- 34 -
NOTE
NOTE
2, 4
2, 4
2, 4
2, 4
2
2
2
3
3
2
2
2
3
3
3. Refer to Table 3 for valid A
4. V
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
word write, or lock-bit configuration.
should be held at V
word write, or lock-bit configuration success (SR.1/3/4/5 = 0).
LH28F800SGH-L70
LH28F800SGH-L70
PP
LH28F800SG-L70
LH28F800SG-L70
MIN.
MIN.
100
100
100
100
100
10
50
50
50
10
30
85
10
50
50
50
10
30
1
5
5
0
0
1
5
5
0
0
0
0
should be held at V
MAX.
MAX.
100
100
HH
) until determination of block erase,
PPH1/2/3
LH28F800SGH-L10 UNIT
LH28F800SGH-L10 UNIT
LH28F800SG-L10
LH28F800SG-L10
MIN.
MIN.
120
100
100
100
100
100
IN
10
50
50
50
10
30
10
50
50
50
10
30
1
5
5
0
0
0
1
5
5
0
0
0
and D
(and if necessary RP#
(NOTE 1)
IN
MAX.
MAX.
for block erase,
100
100
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns