LH28F800 Sharp Electrionic Components, LH28F800 Datasheet - Page 13

• Manufacturer Part Number: LH28F800
• Description: 8 M-bit (512 kB x 16) SmartVoltage Flash Memories
• Manufacturer: Sharp Electrionic Components

the device automatically outputs status register data
when read (see Fig. 3). The CPU can detect block
erase completion by analyzing the output data of
the RY/BY# pin or status register bit SR.7.
When the block erase is complete, status register
bit SR.5 should be checked. If a block erase error
is detected, the status register should be cleared
before system software attempts corrective actions.
The CUI remains in read status register mode until
a new command is issued.
This two-step command sequence of set-up
followed by execution ensures that block contents
are not accidentally erased. An invalid Block Erase
command sequence will result in both status
register bits SR.4 and SR.5 being set to "1". Also,
reliable block erasure can only occur when V
V
this high voltage, block contents are protected
against erasure. If block erase is attempted while
V
Successful
corresponding block lock-bit be cleared or, if set,
that WP# = V
attempted when the corresponding block lock-bit is
set and WP# = V
will be set to "1". Once permanent lock-bit is set,
the blocks which have been set block lock-bit are
unable to erase forever. Block erase operations
with V
should not be attempted.
4.6 Word Write Command
Word write is executed by a two-cycle command
sequence. Word write setup (standard 40H or
alternate 10H) is written, followed by a second write
that specifies the address and data (latched on the
rising edge of WE#). The WSM then takes over,
controlling the word write and write verify algorithms
internally. After the word write sequence is written,
the device automatically outputs status register data
when read (see Fig. 4). The CPU can detect the
CC1/2/3/4
PP
≤ V
IH
< RP# < V
PPLK
and V
, SR.3 and SR.5 will be set to "1".
block
IH
PP
or RP# = V
IL
HH
and RP# = V
= V
erase
produce spurious results and
PPH1/2/3
HH
requires
. In the absence of
. If block erase is
IH
, SR.1 and SR.5
that
CC
the
=
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completion of the word write event by analyzing the
RY/BY# pin or status register bit SR.7.
When word write is complete, status register bit
SR.4 should be checked. If word write error is
detected, the status register should be cleared. The
internal WSM verify only detects errors for "1"s that
do not successfully write to "0"s. The CUI remains
in read status register mode until it receives another
command.
Reliable word writes can only occur when V
V
this high voltage, memory contents are protected
against word writes. If word write is attempted while
V
be set to "1". Successful word write requires that
the corresponding block lock-bit be cleared or, if
set, that WP# = V
attempted when the corresponding block lock-bit is
set and WP# = V
will be set to "1". Once permanent lock-bit is set,
the blocks which have been set block lock-bit are
unable to write forever. Word write operations with
V
should not be attempted.
4.7 Block Erase Suspend Command
The Block Erase Suspend command allows block
erase interruption to read or word write data in
another block of memory. Once the block erase
process starts, writing the Block Erase Suspend
command requests that the WSM suspend the
block erase sequence at a predetermined point in
the algorithm. The device outputs status register
data when read after the Block Erase Suspend
command is written. Polling status register bits
SR.7 and SR.6 can determine when the block
erase operation has been suspended (both will be
set to "1"). RY/BY# will also transition to V
Specification t
suspend latency.
CC1/2/3/4
PP
IH
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
< RP# < V
≤ V
PPLK
and V
, status register bits SR.3 and SR.4 will
WHRH2
HH
PP
IL
IH
and RP# = V
= V
produce spurious results and
or RP# = V
PPH1/2/3
defines the block erase
. In the absence of
HH
IH
, SR.1 and SR.4
. If word write is
CC
OH
=
.