CS8900-CQ3 Cirrus Logic, CS8900-CQ3 Datasheet - Page 93

• Manufacturer Part Number: CS8900-CQ3
• Description: Crystal LAN ISA Ethernet Controller
• Manufacturer: Cirrus Logic

DS271PP3
In the interrupt service routine, the BufEvent regis-
ter (register C), bit RxDMA Frame (bit 7) indicates
that one or more receive frames were transferred
using DMA. The software driver should maintain a
pointer (e.g. PDMA_START) that will point to the
beginning of a new frame. After the CS8900A is
initialized and before any frame is received, pointer
PDMA_START points to the beginning of the
DMA buffer memory area. The first read of the
DMA Frame Count, CDMA, commits the memory
covered by the CDMA count, and the DMA cannot
overwrite this committed space until the space is
freed. The driver then processes the frames de-
scribed by the CDMA count and makes a second
read of the DMA frame count. This second read
frees the buffer memory space described by the
CDMA counter.
CS8900A
Crystal LAN™ ISA Ethernet Controller
"Holes" due to
Base Address
double-word
DMA Buffer
alignment
Figure 24. Example of Frames Stored in DMA Buffer
CIRRUS LOGIC PRODUCT DATA SHEET
RxStatus - Frame 1
RxLength - Frame 1
RxStatus - Frame 3
RxLength - Frame 3
RxStatus - Frame 2
RxLength - Frame 2
Frame 3
Frame 1
During the frame processing, the software should
advance the PDMA_START pointer. At the end of
processing a frame, pointer PDMA_START
should be made to align with a double-word bound-
ary. The software remains in the loop until the
DMA frame count read is zero.
5.5 Auto-Switch DMA
5.5.1 Overview
The CS8900A supports a unique feature, Auto-
Switch DMA, that allows it to switch between
Memory or I/O mode and Receive DMA automati-
cally. Auto-Switch DMA allows the CS8900A to
realize the performance advantages of Memory or
I/O mode while minimizing the number of missed
frames that could result due to slow processing by
the host.
Frame 2
register (PacketPage
DMA Start of Frame
base + 0126H)
points here.
(PacketPage base + 012Ah)
DMA Byte Count
93