CS8900-CQ3 Cirrus Logic, CS8900-CQ3 Datasheet - Page 13

• Manufacturer Part Number: CS8900-CQ3
• Description: Crystal LAN ISA Ethernet Controller
• Manufacturer: Cirrus Logic

DS271PP3
ISA Bus Interface
SA[0:19] - System Address Bus, Input PINS 37-48, 50-54, 58-60.
SD[0:15] - System Data Bus, Bi-Directional with 3-State Output PINS 65-68, 71-74, 27-24, 21-18.
RESET - Reset, Input PIN 75.
AEN - Address Enable, Input PIN 63.
MEMR - Memory Read, Input PIN 29.
MEMW - Memory Write, Input PIN 28.
MEMCS16 - Memory Chip Select 16-bit, Open Drain Output PIN 34.
REFRESH - Refresh, Input PIN 49.
IOR - I/O Read, Input PIN 61.
IOW - I/O Write, Input PIN 62.
CS8900A
Crystal LAN™ ISA Ethernet Controller
Lower 20 bits of the 24-bit System Address Bus used to decode accesses to CS8900A I/O and
Memory space, and attached Boot PROM. SA0-SA15 are used for I/O Read and Write
operations. SA0-SA19 are used in conjunction with external decode logic for Memory Read
and Write operations.
Bi-directional 16-bit System Data Bus used to transfer data between the CS8900A and the host.
Active-high asynchronous input used to reset the CS8900A. Must be stable for at least 400 ns
before the CS8900A recognizes the signal as a valid reset.
When TEST is high, this active-high input indicates to the CS8900A that the system DMA
controller has control of the ISA bus. When AEN is high, the CS8900A will not perform slave
I/O space operations. When TEST is low, this pin becomes the shift clock input for the
Boundary Scan Test. AEN should be inactive when performing an IO or memory access and it
should be active during a DMA cycle.
Active-low input indicates that the host is executing a Memory Read operation.
Active-low input indicates that the host is executing a Memory Write operation.
Open-drain, active-low output generated by the CS8900A when it recognizes an address on the
ISA bus that corresponds to its assigned Memory space (CS8900A must be in Memory Mode
with the MemoryE bit (Register 17, BusCTL, Bit A) set for MEMCS16 to go active). 3-Stated
when not active.
Active-low input indicates to the CS8900A that a DRAM refresh cycle is in progress. When
REFRESH is low, MEMR, MEMW, IOR, IOW, DMACK0, DMACK1, and DMACK2 are
ignored.
When IOR is low and a valid address is detected, the CS8900A outputs the contents of the
selected 16-bit I/O register onto the System Data Bus. IOR is ignored if REFRESH is low.
When IOW is low and a valid address is detected, the CS8900A writes the data on the System
Data Bus into the selected 16-bit I/O register. IOW is ignored if REFRESH is low.
CIRRUS LOGIC PRODUCT DATA SHEET
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