WM8580AGEFTRV WOLFSON [Wolfson Microelectronics plc], WM8580AGEFTRV Datasheet - Page 89

• Manufacturer Part Number: WM8580AGEFTRV
• Description: Multichannel CODEC with S/PDIF Transceiver
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

Production Data
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REGISTER
ADDRESS
PWRDN 1
PWRDN 2
R50
R51
32h
33h
BIT
5:4
4:2
2
3
6
0
1
6
0
1
2
3
4
5
REC_FREQ
DACPD[2:0]
ALLDACPD
SPDIFRXD
SPDIFTXD
SPDIFPD
DEEMPH
UNLOCK
PLLAPD
PLLBPD
OSCPD
ADCPD
LABEL
CPY_N
PWDN
[1:0]
DEFAULT
111
--
0
1
1
0
1
1
1
1
1
-
-
-
Recovered Channel Status bit-2.
Note this signal is inverted and will cause an interrupt on logic 0.
Recovered Channel Status bit-3
Indicates recovered S/PDIF clock frequency:
Indicates that the S/PDIF Clock Recovery circuit is unlocked or
that the input S/PDIF signal is not present.
Chip Powerdown Control (works in tandem with the other
powerdown registers):
ADC powerdown:
DAC powerdowns (0 = DAC enabled, 1 = DAC disabled)
DACPD[0] = DAC1
DACPD[1] = DAC2
DACPD[2] = DAC3
Overrides DACPD[3:0]
OSC power down
0 = PLLA enabled
1 = PLLA disabled
0 = PLLB enable
1 = PLLB disable
S/PDIF Clock Recovery PowerDown
S/PDIF Transmitter powerdown
S/PDIF Receiver powerdown
0 = Copyright is asserted for this data.
1 = Copyright is not asserted for this data.
0 = Recovered S/PDIF data has no pre-emphasis.
1 = Recovered S/PDIF data has pre-emphasis
00 = Invalid
01 = 96kHz / 88.2kHz
10 = 48kHz / 44.1kHz
11 = 32kHz
0 = Locked onto incoming S/PDIF stream.
1 = Not locked to the incoming S/PDIF stream or the incoming
S/PDIF stream is not present.
0 = All digital circuits running, outputs are active
1 = All digital circuits in power save mode, outputs muted
0 = ADC enabled
1 = ADC disabled
0 = S/PDIF enabled
1 = S/PDIF disabled
0 = S/PDIF Transmitter enabled
1 = S/PDIF Transmitter disabled
0 = S/PDIF Receiver enabled
1 = S/PDIF Receiver disabled
0 = DACs under control of DACPD[3:0]
1= All DACs are disabled.
0 = OSC enabled
1 = OSC disabled
DESCRIPTION
PD Rev 4.3 August 2007
WM8580
89