WM8580AGEFTRV WOLFSON [Wolfson Microelectronics plc], WM8580AGEFTRV Datasheet
WM8580AGEFTRV
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WM8580AGEFTRV Summary of contents
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Multichannel CODEC with S/PDIF Transceiver DESCRIPTION The WM8580 is a multi-channel audio CODEC with S/PDIF transceiver. The WM8580 is ideal for DVD and surround sound processing applications for home hi-fi, automotive and other audiovisual equipment. Integrated into the device ...
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WM8580 BLOCK DIAGRAM w Production Data PD Rev 4.3 August 2007 2 ...
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Production Data DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................2 TABLE OF CONTENTS .........................................................................................3 PIN CONFIGURATION...........................................................................................4 ORDERING INFORMATION ..................................................................................4 PIN DESCRIPTION ................................................................................................5 MULTI-FUNCTION PINS............................................................................................... 6 ABSOLUTE MAXIMUM RATINGS.........................................................................8 RECOMMENDED OPERATING CONDITIONS .....................................................9 ELECTRICAL CHARACTERISTICS ......................................................................9 TERMINOLOGY .......................................................................................................... 12 MASTER CLOCK ...
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WM8580 PIN CONFIGURATION ORDERING INFORMATION TEMPERATURE DEVICE RANGE WM8580AGEFT/V -40 to +85 WM8580AGEFT/RV -40 to +85 Note: Reel quantity = 2,200 w PACKAGE 48-lead TQFP o C (Pb-free) 48-lead TQFP o C (Pb-free, tape and reel) Production Data PEAK MOISTURE ...
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Production Data PIN DESCRIPTION PIN NAME 1 PGND 2 PVDD 3 XTI 4 XTO 5 MFP10 6 MFP9 7 MFP8 Digital Input/Output 8 MFP7 Digital Input/Output 9 MFP6 Digital Input/Output 10 SPDIFOP 11 MFP5 Digital Input/Output 12 MFP4 Digital Input/Output ...
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WM8580 PIN NAME 47 VOUT3L Analogue Output 48 VOUT3R Analogue Output Notes : 1. Digital input pins have Schmitt trigger input buffers. Pins 32, 33, 34 are 5V tolerant hardware control mode, pin 30 is used for UNLOCK ...
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Production Data Notes for MFP1: ADC_CLKSEL selected in REG 8, default is ADC_MCLK. PAIFTXMS_CLKSEL selects PLLACLK if PAIF sources SPDIF Rx, otherwise PAIFTXMS_CLKSEL selects ADC_CLK (register 8) 3. MFP2 usage can be described as follows: IF (ADC_CLKSEL ≠ ADCMCLK) AND ...
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WM8580 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics ...
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Production Data RECOMMENDED OPERATING CONDITIONS PARAMETER Digital supply range Analogue supply range PLL supply range Ground AGND, VREFN, DGND. Difference DGND to AGND/PGND Note: Digital supply DVDD must never be more than 0.3V greater than AVDD. ELECTRICAL CHARACTERISTICS Test Conditions ...
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WM8580 Test Conditions AVDD, PVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, PGND, DGND = 0V, T Bit Data, Slave Mode, MCLK, ADCMCLK = 256fs, 1V PARAMETER Power Supply Rejection Ratio (See note 4) ADC Performance Full ...
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Production Data Test Conditions AVDD, PVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, PGND, DGND = 0V, T Bit Data, Slave Mode, MCLK, ADCMCLK = 256fs, 1V PARAMETER Analogue Reference Levels Reference voltage Potential divider resistance S/PDIF ...
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WM8580 TERMINOLOGY 1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). 2. ...
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Production Data DIGITAL AUDIO INTERFACE – MASTER MODE PAIFRX_BCLK/ PAIFTX_BCLK/ SAIF_BCLK (Output) PAIFRX_LRCLK/ PAIFTX_LRCLK/ SAIF_LRCLK (Outputs) DOUT/ SAIF_DOUT DIN1/2/3 SAIF_DIN Figure 2 Digital Audio Data Timing – Master Mode Test Conditions AVDD, PVDD, VREFP = 5V, DVDD = 3.3V, AGND, ...
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WM8580 DIGITAL AUDIO INTERFACE – SLAVE MODE PAIFTX_BCLK/ PAIFRX_BCLK/ SAIF_BCLK PAIFTX_LRCLK/ PAIFRX_LRCLK/ SAIF_BCLK DIN1/2/3/ SAIF_DIN DOUT/ SAIF_DOUT Figure 3 Digital Audio Data Timing – Slave Mode Test Conditions AVDD, PVDD = 5V, DVDD = 3.3V, AGND = 0V, PGND,DGND = ...
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Production Data CONTROL INTERFACE TIMING – 3-WIRE MODE t CSS CSB SCLK SDIN SDO Figure 4 SPI Compatible Control Interface Input Timing Test Conditions AVDD, PVDD = 5V,DVDD = 3.3V, AGND, PGND,DGND = 0V, T otherwise stated PARAMETER SCLK rising ...
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WM8580 CONTROL INTERFACE TIMING – 2-WIRE MODE t 3 SDIN t 6 SCLK t 1 Figure 5 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions AVDD, PVDD = 5V,DVDD = 3.3V, AGND, PGND,DGND = 0V, T otherwise stated ...
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Production Data DEVICE DESCRIPTION INTRODUCTION WM8580 is a complete mutli-channel CODEC with integrated S/PDIF transceiver. comprises three separate stereo DACs and a stereo ADC single package, and controlled by either software or hardware interfaces. The three stereo DAC ...
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WM8580 CONTROL INTERFACE OPERATION Control of the WM8580 is implemented either in Hardware Control Mode or Software Control Mode. The method of control is determined by the state of the HWMODE pin. If the HWMODE pin is low, Software Control ...
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Production Data With CONTREAD set, a single read-only register can be read back by writing to any other register dummy register. The register to be read is determined by the READMUX[2:0] bits. When a write to the ...
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WM8580 Figure 8 3-Wire SPI Compatible Control Interface Non-Continuous Readback 2-WIRE SERIAL CONTROL MODE WITH READ-BACK The WM8580 supports software control via a 2-wire read/write serial bus. Many devices can be controlled by the same bus, and each device has ...
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Production Data REGISTER READBACK The WM8580 allows readback of certain registers in 2-wire mode, with data output on the SDO pin 3-wire mode, there are two methods of reading back data: continuous and non-continuous readback. Continuous readback is ...
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WM8580 DIGITAL AUDIO INTERFACES Audio data is transferred to and from the WM8580 via the digital audio interfaces. There are two receive audio interfaces and two transmit audio interfaces. The digital routing options for these interfaces are described on page ...
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Production Data REGISTER ADDRESS R9 PAIF 1 09h R10 PAIF 2 0Ah R11 SAIF 1 0Bh Table 12 Master Mode Registers The frequency of a master mode LRCLK is dependant on system clock and the RATE register control bits. Table ...
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WM8580 REGISTER ADDRESS R9 PAIF 1 09h R10 PAIF 2 0Ah R11 SAIF 1 0Bh Table 15 Master Mode BCLK Control AUDIO DATA FORMATS Five popular interface formats are supported: • Left Justified mode • Right Justified mode 2 • ...
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Production Data In DSP modes A and B, left and right channels must be time multiplexed and input on the input data line on the Audio Interface. For the PAIF Receiver, all three left/right DAC channels are multiplexed on DIN1 ...
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WM8580 MODE mode, the MSB of DIN1/2/3 is sampled on the second rising edge of BCLK following a LRCLK transition. The MSB of the output data changes on the first falling edge of ...
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Production Data The MSB of the left channel of the output data changes on the first falling edge of BCLK following a low to high LRCLK transition and may be sampled on the rising edge of BCLK. The right channel ...
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WM8580 The MSB of the output data changes on the same falling edge of BCLK as the low to high LRCLK transition and may be sampled on the rising edge of BCLK. The right channel data is contiguous with the ...
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Production Data REGISTER ADDRESS R13 PAIF 4 0Dh R14 SAIF 2 0Eh Table 16 Audio Interface Control Notes 1. Right Justified mode does not support 32-bit data. If word length xAIFxxWL=11b in Right Justified mode, the word length is forced ...
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WM8580 bit I a minimum of 24 BCLK cycles and low for a minimum of 24 BCLK cycles. If exactly 32 bit clocks occur in one full left/right clock period the interface will auto detect and configure ...
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Production Data DAC OUTPUT CONTROL The DAC output control word determines how the left and right inputs to the audio interface are applied to the left and right DACs: REGISTER ADDRESS DAC Control 2 Table 19 DAC Attenuation Register (PL) ...
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WM8580 INFINITE ZERO DETECT Setting the IZD register bit will enable the internal Infinite Zero Detect function: REGISTER ADDRESS DAC Control 2 Table 21 IZD Register With IZD enabled, applying 1024 consecutive zero input samples to a stereo input channel ...
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Production Data DAC DIGITAL VOLUME CONTROL The DAC volume may also be adjusted in the digital domain using independent digital attenuation control registers REGISTER BIT LABEL ADDRESS R20 7:0 LDA1[7:0] Digital Attenuation 8 UPDATE DACL 1 14h R21 7:0 RDA1[6:0] ...
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WM8580 L/RDAx[7:0] Table 23 Digital Volume Control Gain Levels Setting the DACATC register bit causes the left channel attenuation settings to be applied to both left and right channel DACs from the next audio input sample. No update to the ...
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Production Data MUTE MODES The WM8580 has individual mutes for each of the three DAC channels. Setting DMUTE for a channel will apply a ‘soft-mute’ to the input of the digital filters for that channel. DMUTE[0] mutes DAC1 channel, DMUTE[1] ...
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WM8580 1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 0 Figure 23 Application and Release of Mute w 0.001 0.002 0.003 Time(s) Production Data 0.004 0.005 0.006 PD Rev 4.3 August 2007 36 ...
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Production Data DMUTE(2:0) DACPD(2:0) PL(3:0) MUTEALL MUTE (register) Decode MPDENB MUTE (pin) DAC1 i/p 1024 Zeros DAC2 i/p Detect DAC3 i/p Figure 24 Mute Mode Block Diagram Note: The above block diagram shows the operation of the various mute functions. ...
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WM8580 Figure 23 shows the application and release of MUTE whilst a full amplitude sinusoid is being played at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace) begins to decay exponentially from the DC level ...
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Production Data ADC FEATURES ADC HIGH-PASS FILTER DISABLE The ADC digital filters incorporate a digital high-pass filter. By default, this is enabled but can be disabled by setting the ADCHPD register bit to 1. This allows the input to the ...
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WM8580 DIGITAL ROUTING OPTIONS The WM8580 has extremely flexible digital interface routing options, which are illustrated in Figure 25. It has S/PDIF Receiver, S/PDIF Transmitter, 3 Stereo DACs, a Stereo ADC, a Primary Audio Interface and a Secondary Audio Interface. ...
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Production Data The registers described below configure the digital routing options. REGISTER ADDRESS R12 PAIF 3 0Ch R13 PAIF 4 0Dh R14 SAIF 2 0Eh R30 SPDTXCHAN 0 1Eh Table 32 Interface Source Select Registers w BIT LABEL DEFAULT 8:7 ...
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WM8580 CLOCK SELECTION To accompany the flexible digital routing options, the WM8580 offers a clock configuration scheme for each interface. By default, the user can choose the interface clock from MCLK, ADCMCLK, PLLACLK or PLLBCLK, with some restrictions which are ...
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Production Data REGISTER ADDRESS R8 CLKSEL 08h R15 DAC Control 1 0Fh Table 33 DAC Clock Control ADC INTERFACE The ADC_CLKSEL register selects the ADC clock source from ADCMCLK, PLLACLK, PLLBCLK, or MCLK. However, if the S/PDIF receiver is active, ...
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WM8580 REGISTER ADDRESS R8 CLKSEL 08h R29 ADC Control 1 1Dh Table 34 ADC Clock Control S/PDIF INTERFACES The TX_CLKSEL register selects the clock for the S/PDIF Transmitter from ADCMCLK, PLLACLK, PLLBCLK, or MCLK. The S/PDIF Receiver only uses PLLACLK, ...
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Production Data REGISTER ADDRESS R8 CLKSEL 08h Table 35 S/PDIF Transmitter Clock Control PRIMARY AUDIO INTERFACE RECEIVER (PAIF RX) The PAIF Receiver requires a left-right-clock (LRCLK) and a bit-clock (BCLK). These can be supplied externally (slave mode) or they can ...
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WM8580 PRIMARY AUDIO INTERFACE TRANSMITTER (PAIF TX) The PAIF Transmitter requires a left-right-clock (LRCLK) and a bit-clock (BCLK). These can be supplied externally (slave mode) or they can be generated internally by the WM8580 (master mode). The master mode LRCLK/BCLK ...
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Production Data REGISTER ADDRESS R11 SAIF 1 0Bh Table 37 SAIF Master Mode Clock Control MANUAL CLOCK SELECTION It is possible to override all default clocking configuration restrictions by setting CLKSEL_MAN. When CLKSEL_MAN is set, default clocking configurations such as ...
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WM8580 PHASE-LOCKED LOOPS AND S/PDIF CLOCKING (SOFTWARE MODE) The WM8580 is equipped with two independent phase-locked loop clock generators and a comprehensive clocking scheme which provides maximum flexibility and function and many configurable routing possibilities for the user in software ...
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Production Data The oscillator XOUT pin has one control bit as shown in Table 39. REGISTER ADDRESS R51 PWRDN 2 33h Table 39 Oscillator Control PHASE-LOCKED LOOP (PLL) The WM8580 has two on-chip phase-locked loop (PLL) circuits which can be ...
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WM8580 • PLL User Mode (Selected if S/PDIF Receiver Disabled) In user mode, the user has full control over the function and operation of both PLLA and PLLB. In this mode, the user can accurately specify the PLL N and ...
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Production Data PLL CONFIGURATION The PLLs perform a configurable frequency multiplication of the input clock signal (f multiplication factor of the PLL (denoted by ‘R’) is variable and is defined by the relationship The ...
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WM8580 FREQMODE_x[1:0] Table 44 PLL User Mode Clock Divider Configuration POSTSCALE_A Table 45 PLL S/PDIF Receiver Mode Clock Divider Configuration PLL CONFIGURATION EXAMPLE Consider the situation where the oscillator clock (OSCCLK) input frequency is fixed at 12MHz and the required ...
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Production Data OSC PRE SCALE CLK (MHz) _x (MHz 90.3168 90.3168 ...
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WM8580 S/PDIF RECEIVE MODE CLOCKING In S/PDIF receive mode, the PLLA_N and PLLA_K values are automatically controlled by the S/PDIF receiver to allow the receiver to use PLLA to lock on to and track the incoming S/PDIF data stream. PLLB ...
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Production Data PHASE-LOCKED LOOPS AND S/PDIF CLOCKING (HARDWARE MODE) In hardware mode, the user has no access to the internal clocking control registers and hence a default configuration is loaded at reset to provide maximum functionality. The S/PDIF receiver is ...
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WM8580 Frame 0 Sync preamble Figure 33 S/PDIF Format S/PDIF TRANSMITTER The S/PDIF transmitter generates the S/PDIF frames, and outputs on the SPDIFOP pin. The audio data for the frame can be taken from one of four sources, selectable using ...
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Production Data The WM8580 also transmits the preamble and VUCP bits (Validity, User Data, Channel Status and Parity bits). Validity Bit By default, set to 0 (to indicate valid data) with the following exceptions: 1. TXSRC=00 (S/PDIF receiver), where Validity ...
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WM8580 REGISTER BIT ADDRESS R32 7:0 CATCODE SPDTXCHAN 2 20h Table 51 S/PDIF Transmitter Channel Status Bit Control 2 REGISTER BIT ADDRESS R33 3:0 SPDTXCHAN 3 21h 5:4 CHNUM1[1:0] 7:6 CHNUM2[1:0] Table 52 S/PDIF Transmitter Channel Status Bit Control 3 ...
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Production Data REGISTER BIT ADDRESS R35 0 SPDTXCHAN 5 23h 3:1 TXWL[2:0] 7:4 ORGSAMP Table 54 S/PDIF Transmitter Channel Status Bit Control 5 S/PDIF RECEIVER INPUT SELECTOR The S/PDIF receiver has one dedicated input, SPDIFIN1. This pin is a IEC-60958-3-compatible ...
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WM8580 REGISTER BIT ADDRESS R36 0 SPDMODE 24h 2:1 6 R39 3:0 GPO2 7:4 26h R40 3:0 GPO3 27h R51 5 PWRDN 2 33h Table 55 S/PDIF Receiver Input Selection Register AUDIO DATA HANDLING The S/PDIF receiver recovers the data ...
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Production Data The audio data sample can be transferred to either the AIF or the SPDIF Tx. When the audio data sample is transferred to the AIF, and if the AIF is operating in a mode which has less data ...
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WM8580 REGISTER BIT ADDRESS R46 3:0 SPDRXCHAN 3 2Eh 5:4 CHNUM1[1:0] (read-only) 7:6 CHNUM2[1:0] Table 58 S/PDIF Receiver Channel Status Register 3 REGISTER BIT ADDRESS R47 3:0 SPDRXCHAN 4 2Fh 5:4 CLKACU[1:0] (read-only) Table 59 S/PDIF Receiver Channel Status Register ...
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Production Data STATUS FLAGS There are several status flags generated by the S/PDIF Receiver, described below. FLAG UNLOCK Indicates that the S/PDIF Clock Recovery circuit is unlocked, or the incoming S/PDIF signal is not present Locked onto incoming ...
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WM8580 INTERRUPT GENERATION (INT_N) The hardware interrupot INT_N flag (active low) indicates that a change of status has occurred on one or more of the UNLOCK, INVALID, TRANS_ERR, NON_AUDIO, CPY_N, DEEMPH, CSUD or REC_FREQ flags. To determine which flag caused ...
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Production Data REGISTER BIT ADDRESS R49 0 SPDSTAT 31h (read-only 5:4 REC_FREQ 6 Table 63 S/PDIF Status Register The interrupt and update signals used to generate INT_N can be masked as necessary. The MASK register bit prevents ...
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WM8580 ERROR HANDLING IN SOFTWARE MODE When the TRANS_ERR flag is asserted, it indicates that the recovered Rx S/PDIF sub-frame is corrupted. This corruption can due to a BI-Phase error, a parity error or a pre-amble error.When the INVALID flag ...
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Production Data NON-AUDIO DETECTION The SPDIF payload can contain PCM data for audio or non-audio applications. In the case where the payload contains the 96 bit synchronization code defined in IEC61937 then this indicates that the payload contains data which ...
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WM8580 POWERDOWN MODES The WM8580 has powerdown control bits allowing specific parts of the chip to be turned off when not in use. The ADC is powered down by setting the ADCPD register bit. The three stereo DACs each have ...
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Production Data REGISTER ADDRESS Table 67 Powerdown Registers w BIT LABEL R50 0 PWDN PWRDN 1 32h 1 ADCPD 4:2 DACPD[2:0] 6 ALLDACPD R51 0 OSCPD PWRDN 2 33h 1 PLLAPD 2 PLLBPD 3 SPDIFPD 4 SPDIFTXD 5 SPDIFRXD WM8580 ...
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WM8580 INTERNAL POWER ON RESET CIRCUIT Figure 34 Internal Power On Reset Circuit Schematic The WM8580 includes an internal Power-On Reset Circuit, which is used to reset the digital logic into a default state after power up. Figure 34 shows ...
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Production Data Figure 35 Typical Power up Sequence where DVDD is Powered before AVDD Figure 36 Typical Power up Sequence where AVDD is Powered before DVDD SYMBOL V pora V porr V pora_off V pord_off Table 68 Typical POR Operation ...
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WM8580 Figure 35 and Figure 36 show typical power up scenarios in a real system. Both AVDD and DVDD must be established, and VMID must have reached the threshold Vporr before the device is ready and can be written to. ...
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Production Data Table 71 DR3 / DR4 Operation The Secondary Audio Interface (SAIF) is not operational in Hardware Mode. STATUS PINS In Hardware control mode, SDO, SWMODE and MFP8/9/10 pins provide S/PDIF status flag information. PIN SWMODE SDO MFP8 MFP9 ...
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WM8580 MUTE Floating Table 74 MUTE Pin Control Options PRIMARY AUDIO INTERFACE (TX) MASTER MODE CONTROL In Hardware Control Mode, the SDIN pin is used to enable the master mode function on the Primary Audio Interface transmitter. This has the ...
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Production Data REGISTER MAP The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The WM8580 can be configured using the Control Interface. All unused bits should be set ...
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WM8580 REGISTER NAME ADDRESS R39 27 GPO2 R40 28 GPO3 R41 29 GPO4 R42 2A GPO5 R43 2B INTSTAT R44 2C SPDRXCHAN 1 R45 2D SPDRXCHAN 2 R46 2E SPDRXCHAN 3 R47 2F SPDRXCHAN 4 R48 30 SPDRXCHAN 5 R49 ...
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Production Data REGISTER BIT LABEL ADDRESS R4 8:0 PLLB_K[8:0] PLLB 1 04h R5 8:0 PLLB_K[17:9] PLLB 2 05h R6 3:0 PLLB_K[21:18] PLLB 3 7:4 PLLB_N[3:0] 06h R7 0 PRESCALE_B PLLB 4 07h 1 POSTSCALE_B 4:3 FREQMODE_B [1:0] 6:5 MCLKOUTSRC 8:7 ...
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WM8580 REGISTER BIT LABEL ADDRESS 5:4 TX_CLKSEL 6 CLKSEL_MAN R9 2:0 PAIFRX_RATE PAIF 1 [2:0] 09h 4:3 PAIFRX_BCLKSEL [1:0] 5 PAIFRXMS 7:6 PAIFRXMS_ CLKSEL R10 2:0 PAIFTX_RATE PAIF 2 [2:0] 0Ah 4:3 PAIFTX_BCLKSEL [1:0] 5 PAIFTXMS w DEFAULT 01 S/PDIF ...
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Production Data REGISTER BIT LABEL ADDRESS R11 2:0 SAIF_RATE SAIF1 [2:0] 0Bh 4:3 SAIF_BCLKSEL [1:0] 5 SAIFMS 7:6 SAIFMS_ CLKSEL [1:0] R12 1:0 PAIFRXFMT PAIF 3 [1:0] 0Ch 3:2 PAIFRXWL [1:0] 4 PAIFRXLRP 5 PAIFRXBCP 6 DACOSR 8:7 DAC_SRC [1:0] ...
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WM8580 REGISTER BIT LABEL ADDRESS R13 1:0 PAIFTXFMT PAIF 4 [1:0] 0Dh 3:2 PAIFTXWL [1:0] 4 PAIFTXLRP 5 PAIFTXBCP 8:7 PAIFTX_SRC [1:0] R14 1:0 SAIFFMT SAIF 2 [1:0] 0Eh 3:2 SAIFWL [1:0] 4 SAIFLRP 5 SAIFBCP 6 SAIF_EN 8:7 SAIFTX_SRC ...
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Production Data REGISTER BIT LABEL ADDRESS R15 1:0 DAC1SEL DAC [1:0] Control 1 3:2 DAC2SEL 0Fh [1:0] 5:4 DAC3SEL [1:0] 8 RX2DAC_MODE R16 3:0 PL[3:0] DAC Control 2 10h 6:4 DZFM[2:0] 7 IZD R17 2:0 DEEMP[2:0] DAC Control 3 11h ...
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WM8580 REGISTER BIT LABEL ADDRESS R18 5:0 PHASE [5:0] DAC Control 4 12h R19 2:0 DMUTE[2:0] DAC Control 5 13h 4 MUTEALL 5 DZCEN 6 DACATC 7 MPDENB 7:0 LDA1[7:0] R20 Digital Attenuation 8 UPDATE DACL 1 14h R21 7:0 ...
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Production Data REGISTER BIT LABEL ADDRESS Attenuation 8 UPDATE DACR 3 19h R28 7:0 MASTDA[7:0] Master Digital Attenuation 8 UPDATE 1Ch R29 0 AMUTEL ADC Control 1 1Dh 1 AMUTER 2 AMUTEALL 3 ADCOSR 4 ADCHPD 7:5 ADCRATE[2:0] 8 VMIDSEL ...
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WM8580 REGISTER BIT LABEL ADDRESS 4 TXVAL_OVWR 5 TXVAL_SF0 6 TXVAL_SF1 R31 0 CON/PRO SPDTXCHAN 1 1Fh 1 AUDIO_N 2 CPY_N 5:3 DEEMPH[2:0] 7:6 CHSTMODE [1:0] R32 7:0 CATCODE [7:0] SPDTXCHAN 2 20h R33 3:0 SRCNUM [3:0] SPDTXCHAN 3 21h ...
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Production Data REGISTER BIT LABEL ADDRESS R35 0 MAXWL SPDTXCHAN 5 23h 3:1 TXWL[2:0] 7:4 ORGSAMP [3:0] R36 0 SPDIFIN1MODE SPDMODE 24h 2:1 RXINSEL[1:0] 6 WL_MASK R37 8:0 MASK[8:0] INTMASK 25h w DEFAULT 1 Maximum Audio sample word length 0 ...
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WM8580 REGISTER BIT LABEL ADDRESS R38 3:0 GPO1OP[3:0] GPO1 7:4 GPO2OP[3:0] 26h 8 FILLMODE R39 3:0 GPO3OP[3:0] GPO2 7:4 GPO4OP[3:0] 27h 8 ALWAYSVALID w DEFAULT 0000 0000 = INT_N 0001 0001 = V 0010 = U 0011 = C 0100 ...
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Production Data REGISTER BIT LABEL ADDRESS R40 3:0 GPO5OP[3:0] GPO3 7:4 GPO6OP[3:0] 28h R41 3:0 GPO7OP[3:0] GPO4 7:4 GPO8OP[3:0] 29h R42 3:0 GPO9OP[3:0] GPO5 7:4 GPO10OP 2Ah [3:0] R43 0 UPD_UNLOCK INTSTAT 2Bh 1 INT_INVALID 2 INT_CSUD 3 INT_TRANS_ERR 4 ...
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WM8580 REGISTER BIT LABEL ADDRESS 5:4 Reserved 7:6 CHSTMODE [1:0] R45 7:0 CATCODE [7:0] SPDRXCHAN 2 2Dh R46 3:0 SRCNUM [3:0] SPDRXCHAN 3 2Eh 5:4 CHNUM1[1:0] 7:6 CHNUM2[1:0] R47 3:0 FREQ[3:0] SPDRXCHAN 4 2Fh 5:4 CLKACU[1:0] R48 0 MAXWL SPDRXCHAN ...
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Production Data REGISTER BIT LABEL ADDRESS 2 CPY_N 3 DEEMPH 5:4 REC_FREQ [1:0] 6 UNLOCK R50 0 PWDN PWRDN 1 32h 1 ADCPD 4:2 DACPD[2:0] 6 ALLDACPD R51 0 OSCPD PWRDN 2 33h 1 PLLAPD 2 PLLBPD 3 SPDIFPD 4 ...
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WM8580 REGISTER BIT LABEL ADDRESS R52 2:0 READMUX READBACK [2:0] 34h 3 CONTREAD 4 READEN R53 8:0 RESET RESET 35h DIGITAL FILTER CHARACTERISTICS PARAMETER Passband Passband ripple Stopband Stopband Attenuation Passband Passband ripple Stopband Stopband Attenuation Table 77 Digital Filter ...
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Production Data DAC FILTER RESPONSES 0 -20 -40 -60 -80 -100 -120 0 0.5 1 1.5 Frequency (Fs) Figure 37 DAC Digital Filter Frequency Response – 44.1, 48 and 96kHz 0 -20 -40 -60 -80 0 0.2 0.4 Frequency (Fs) ...
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WM8580 DIGITAL DE-EMPHASIS CHARACTERISTICS - Frequency (kHz) Figure 41 De-Emphasis Frequency Response (44.1kHz - Frequency (kHz) Figure 43 De-Emphasis Frequency Response (48kHz) ADC FILTER ...
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Production Data ADC HIGH PASS FILTER The WM8580 has a selectable digital high pass filter to remove DC offsets. The filter response is characterised by the following polynomial. H( 0.9995z 0 -5 -10 -15 0 0.0005 0.001 ...
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WM8580 APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 48 Recommended External Components w Production Data PD Rev 4.3 August 2007 94 ...
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Production Data Figure 49 Recommended External Components w WM8580 PD Rev 4.3 August 2007 95 ...
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WM8580 PACKAGE DIMENSIONS FT: 48 PIN TQFP ( 1.0 mm Dimensions Symbols (mm) MIN NOM A ----- ----- A 0.05 ----- 1 A 0.95 1. ...
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