71M6534 MAXIM [Maxim Integrated Products], 71M6534 Datasheet - Page 47

• Manufacturer Part Number: 71M6534
• Description: Exceeds IEC 62053/ANSI C12.20 Standards
• Manufacturer: MAXIM [Maxim Integrated Products]

Two-pin EEPROM Interface
The dedicated 2-pin serial interface communicates with external EEPROM devices. The interface is
multiplexed onto the DIO4 (SCK) and DIO5 (SDA) pins and is selected by setting DIO_EEX[1:0] = 01.
modes, VBAT in LCD mode). When the LCD_DAC[2:0] bits are set to 000, the DAC is bypassed and
powered down. This can be used to reduce current in LCD mode.
1.5.9 Battery Monitor
The battery voltage is measured by the ADC during alternative MUX frames if the BME (Battery Measure
Enable) bit is set. While BME is set, an on-chip 45 kΩ load resistor is applied to the battery and a scaled
fraction of the battery voltage is applied to the ADC input. After each alternative MUX frame, the result of
the ADC conversion is available at XRAM address 0x07. BME is ignored and assumed zero when system
power is not available.
Battery measurement is not very linear but is very reproducible. The best way to perform the calibration
is to set the battery input to the desired failure voltage and then have the MPU firmware record that
measurement. After this, the MPU firmware’s battery measurement logic may use the recorded value as
the battery failure limit. The same value can also be a calibration offset for any battery voltage display.
See
1.5.10 EEPROM Interface
The 71M6533 and 71M6534 provides hardware support for either a two-pin or a three-wire (µ-wire) type
of EEPROM interface. The interfaces use the EECTRL and EEDATA registers for communication.
The MPU communicates with the interface through the SFR registers EEDATA and EECTRL. If the MPU
wishes to write a byte of data to the EEPROM, it places the data in EEDATA and then writes the Transmit
code to EECTRL. This initiates the transmit operation which is finished when the BUSY bit falls. INT5 is also
asserted when BUSY falls. The MPU can then check the RX_ACK bit to see if the EEPROM acknowledged
the transmission.
A byte is read by writing the Receive command to EECTRL and waiting for the BUSY bit to fall. Upon
completion, the received data is in EEDATA. The serial transmit and receive clock is 78 kHz during each
transmission, and then holds in a high state until the next transmission. The EECTRL bits when the two-pin
interface is selected are shown in
Rev 2
Status
Bit
3:0
7
6
5
4
Section 6.4.5
If VBAT is connected to a drained battery or disconnected, a battery test that sets BME may drain
VBAT’s supply and cause the oscillator to stop. A stopped oscillator may force the device to reset.
Therefore, an unexpected reset during a battery test should be interpreted as a battery failure.
ERROR
BUSY
RX_ACK
TX_ACK
CMD[3:0]
Name
for details regarding the ADC LSB size and the conversion accuracy.
Read/
Write
W
R
R
R
R
Table 44: EECTRL Bits for 2-pin Interface
Reset
State
0000
Table
0
0
1
1
44.
Positive
Positive
Negative
Negative
Positive
Polarity
Description
1 when an illegal command is received.
1 when serial data bus is busy.
0 indicates that the EEPROM sent an ACK bit.
0 indicates when an ACK bit has been sent to the
EEPROM.
0000
0010
0011
0101
CMD[3:0]
No-op command. Stops the I
(SCK, DIO4). If not issued, SCK
keeps toggling.
Receive a byte from the EEPROM
and send ACK.
Transmit a byte to the EEPROM.
Issue a STOP sequence.
Operation
2
C clock
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