71M6534 MAXIM [Maxim Integrated Products], 71M6534 Datasheet - Page 25

• Manufacturer Part Number: 71M6534
• Description: Exceeds IEC 62053/ANSI C12.20 Standards
• Manufacturer: MAXIM [Maxim Integrated Products]

1.4.4 71M6533/71M6534-Specific Special Function Registers
Table 14
Rev 2
EEDATA
EECTRL
ERASE
(FLSH_ERASE)
FL_BANK[2:0]
PGADDR
(FLSH_PGADR)
FLSHCRL
(Alternate Name)
Register
shows the location and description of the 71M6533/71M6534-specific SFRs.
CKCON[2:0]
000
001
010
011
100
101
110
111
0x9E
0x9F
0x94
0xB6[2:0]
0xB7
0xB2[0]
0xB2[1]
0xB2[4]
0xB2[5]
0xB2[6]
0xB2[7]
* The WRPROT_CE and WRPROT_BT bits can only be cleared when the SECURE bit
is not set. When SECURE = 1, WRPROT_CE and WRPROT_BT can only be set to 1.
A hardware reset is required to clear these bits if SECURE = 1.
Address
SFR
Table 14: 71M6533/71M6534 Specific SFRs
Stretch
FLSH_PWE
FLSH_MEEN
WRPROT_CE*
WRPROT_BT*
SECURE
PREBOOT
Table 13: Stretch Memory Cycle Width
Value
0
1
2
3
4
5
6
7
Bit Field
Name
memaddr
Read Signal Width
1
2
3
4
5
6
7
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
R
Description
I
I
See
description of the command and status bits
available for EECTRL.
This register is used to initiate either the Flash
Mass Erase cycle or the Flash Page Erase cycle.
See the
Flash Bank Selection.
Flash Page Erase Address register. Contains
the flash memory page address (page 0
through page 127) that will be erased during the
Page Erase cycle (default = 0x00). Must be re-
written for each new Page Erase cycle.
Program Write Enable:
Mass Erase Enable:
Must be re-written for each new Mass Erase cycle.
Protects flash from address CE_LCTN *1024 to
the end of memory from flash page erase.
Protects flash from address 0 to address
BOOT_SIZE*1024 from flash page erase.
Enables security provisions that prevent external
reading of flash memory and CE program RAM.
This bit is reset on chip reset and may only be set.
Attempts to write zero are ignored.
Indicates that the preboot sequence is active.
memrd
2
2
C EEPROM interface data register.
C EEPROM interface control register.
0: MOVX commands refer to XRAM Space,
1: MOVX @DPTR,A moves A to Program
0: Mass Erase disabled (default).
1: Mass Erase enabled.
1
2
3
4
5
6
7
8
Section 1.5.10
normal operation (default).
Space (Flash) @ DPTR.
Flash Memory
memaddr
Write Signal Width
2
3
4
5
6
7
8
9
EEPROM Interface
section for details.
memwr
1
1
2
3
4
5
6
7
for a
25