71M6534 MAXIM [Maxim Integrated Products], 71M6534 Datasheet - Page 20

• Manufacturer Part Number: 71M6534
• Description: Exceeds IEC 62053/ANSI C12.20 Standards
• Manufacturer: MAXIM [Maxim Integrated Products]

SFR. This method allows the user paged access (256 pages of 256 bytes each) to all ranges of the
external data RAM.
The 80515 writes into external data memory when the MPU executes a MOVX @Ri,A or MOVX
@DPTR,A instruction. The MPU reads external data memory by executing a MOVX A,@Ri or MOVX
A,@DPTR instruction (SFR PDATA provides the upper 8 bytes for the MOVX A,@Ri instruction).
Internal and External Memory Map
Table 7 shows the address, type, use and size of the various memory components.
†
MOVX Addressing
There are two types of instructions differing in whether they provide an 8-bit or 16-bit indirect address to
the external data RAM.
In the first type, MOVX A,@Ri, the contents of R0 or R1 in the current register bank provide the eight
lower-ordered bits of address. The eight high-ordered bits of the address are specified with the PDATA
In the second type of MOVX instruction, MOVX A,@DPTR, the data pointer generates a 16-bit address.
This form is faster and more efficient when accessing very large data arrays (up to 64 KB), since no
additional instructions are needed to set up the eight high ordered bits of the address.
It is possible to mix the two MOVX types. This provides the user with four separate data pointers, two
with direct access and two with paged access, to the entire 64 KB of external memory range.
Dual Data Pointer
The Dual Data Pointer accelerates the block moves of data. The standard DPTR is a 16-bit register that
is used to address external memory or peripherals. In the 80515 core, the standard data pointer is called
DPTR, the second data pointer is called DPTR1. The data pointer select bit, located in the LSB of the DPS
register (DPS[0]), chooses the active pointer. DPTR is selected when DPS[0] = 0 and DPTR1 is selected
when DPS[0] = 1.
20
00000-3FFFF
00000-1FFFF
For the 71M6534 only.
2000-20BF,
20C0-20C7
20C8-20FF
0000-0FFF
0000-00FF
boundary
Address
on 1K
(hex)
If the MPU overwrites the CE’s working RAM, the CE’s output may be corrupted. If the CE is
disabled, the first 0x40 bytes of RAM are still unusable while MUX_DIV[3:0] ≠ 0 because the
71M6533/71M6534 ADC writes to these locations. Setting MUX_DIV[3:0] = 0 disables the ADC
output, preventing the CE from writing the first 0x40 bytes of RAM.
Only the memory ranges shown in
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Flash Memory
Flash Memory
Flash Memory
Technology
Static RAM
Static RAM
Static RAM
Static RAM
Memory
Memory
(battery)
Volatile
Volatile
Volatile
volatile
volatile
volatile
volatile
Type
Non-
Non-
Non-
Non-
Table 7: Memory Map
Table 7
Configuration RAM
Configuration RAM
Program memory
Program memory
Program memory
contain physical memory.
External RAM
Internal RAM
(I/O RAM)
(I/O RAM)
(XRAM)
Name
Part of 80515 Core
MPU Program and
MPU Program and
Shared by CE and
Hardware control
non-volatile data
non-volatile data
Battery-buffered
Typical Usage
CE program
memory
MPU
Memory Size
8 KB max.
256 KB
(bytes)
128 KB
4 KB
256
256
8
Rev 2
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