71M6534 MAXIM [Maxim Integrated Products], 71M6534 Datasheet - Page 27

• Manufacturer Part Number: 71M6534
• Description: Exceeds IEC 62053/ANSI C12.20 Standards
• Manufacturer: MAXIM [Maxim Integrated Products]

WDCON[7] selects whether timer 1 or the internal baud rate generator is used. All UART transfers are
programmable for parity enable, parity, 2 stop bits/1 stop bit and XON/XOFF options for variable
communication baud rates from 300 to 38400 bps.
Table 16
S0REL and S1REL are 10-bit values derived by combining bits from the respective timer reload registers
(S0RELL, S0RELH, S1RELL, S1RELH). SMOD is the SMOD bit in the SFR PCON register. TH1 is the high
byte of timer 1.
The feature of receiving 9 bits (Mode 3 for UART0, Mode A for UART1) can be used as handshake signals
for inter-processor communication in multi-processor systems. In this case, the slave processors have bit
SM20 (S0CON[5]) for UART0, or SM21 (S1CON[5] for UART1, set to 1. When the master processor outputs
the slave’s address, it sets the 9
slave processors compare the received byte with their address. If there is a match, the addressed slave
will clear SM20 or SM21 and receive the rest of the message. The rest of the slave’s will ignore the message.
After addressing the slave, the host outputs the rest of the message with the 9
serial port receive interrupts will be generated.
UART Control Registers:
The functions of UART0 and UART1 depend on the setting of the Serial Port Control Registers S0CON
and S1CON shown in
Rev 2
Mode 0
Mode 1
Mode 2
Mode 3
UART0
UART1
control bits TB80 (S0CON[3]) and TB81 (S1CON[3]) in the S0CON (SFR 0x98) and S1CON (SFR 0x9B)
SFRs for transmit and RB81 (S1CON[2]) for receive operations.
Parity of serial data is available through the P flag of the accumulator. 7-bit serial modes with
parity, such as those used by the FLAG protocol, can be simulated by setting and reading bit 7 of
8-bit output data. 7-bit serial modes without parity can be simulated by setting bit 7 to a constant
1. 8-bit serial modes with parity can be simulated by setting and reading the 9
shows the selectable UART operation modes.
Since the TI0, RI0, TI1 and RI1 bits are in an SFR bit addressable byte, common practice
would be to clear them with a bit operation, but this must be avoided. The hardware implements
bit operations as a byte wide read-modify-write hardware macro. If an interrupt occurs after
the read, but before the write, its flag will be cleared unintentionally.
The proper way to clear these flag bits is to write a byte mask consisting of all ones except for
a zero in the location of the bit to be cleared. The flag bits are configured in hardware to ignore
ones written to them.
N/A
Start bit, 8 data bits, stop bit, variable
baud rate (internal baud rate generator
or timer 1)
Start bit, 8 data bits, parity, stop bit,
fixed baud rate 1/32 or 1/64 of f
Start bit, 8 data bits, parity, stop bit,
variable baud rate (internal baud rate
generator or timer 1)
Table 17
2
N/A
smod
* f
and
CKMPU
UART 0
(WDCON[7] = 0)
th
Using Timer 1
bit to 1, causing a serial port receive interrupt in all the slaves. The
Table 18,
Table 15: Baud Rate Generation
/ (384 * (256-TH1))
Table 16: UART Modes
respectively, and the PCON register shown in
CKMPU
Table 15
Start bit, 8 data bits, parity, stop bit, variable
baud rate (internal baud rate generator)
Start bit, 8 data bits, stop bit, variable baud
rate (internal baud rate generator)
N/A
N/A
2
f
CKMPU
smod
shows how the baud rates are calculated.
Using Internal Baud Rate Generator
* f
/(32 * (2
CKMPU
/(64 * (2
(WDCON[7] = 1)
10
-S1REL))
th
UART 1
bit set to 0, so no additional
10
-S0REL))
th
bit, using the
Table
19.
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