MC9S12A128 MOTOROLA [Motorola, Inc], MC9S12A128 Datasheet - Page 50

• Manufacturer Part Number: MC9S12A128
• Description: Microcontroller unit (MCU)
• Manufacturer: MOTOROLA [Motorola, Inc]

MC9S12A128 Device Guide — V01.01
5.3 Effects of Reset
When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the
respective module Block User Guides for register reset states.
5.3.1 I/O Pins
Refer to the HCS12 Core User Guide (Motorola document order number HCS12COREUG/D) for mode
dependent pin configuration of port A, B, E and K out of reset.
Refer to the MC9S12A128 Port Integration Module (PIM) Block Guide (Motorola document order
number, S12A128PIMV1/D) for reset configurations of all peripheral module ports.
5.3.2 Memory
Refer to
mode after reset.
The RAM array is not automatically initialized out of reset.
$FFC8, $FFC9
$FFC6, $FFC7
$FFC4, $FFC5
$FFC2, $FFC3
$FFC0, $FFC1
$FFBE, $FFBF
$FFBC, $FFBD
$FFBA, $FFBB
$FFB8, $FFB9
$FF90 to
$FFB7
$FF8E, $FF8F
$FF8C, $FF8D
$FF80 to
$FF8B
50
NOTE:
Table 1-1 Device Memory Map
For devices assembled in 80-pin QFP packages all non-bonded out pins should be
configured as outputs after reset in order to avoid current drawn from floating
inputs. Refer to
Pulse Accumulator B Overflow
PWM Emergency Shutdown
CRG Self Clock Mode
Port P Interrupt
CRG PLL lock
Table 2-1 Signal Properties
EEPROM
IIC Bus
FLASH
SPI1
for locations of the memories depending on the operating
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
Reserved
Reserved
Reserved
Reserved
for affected pins.
SP1CR1 (SPIE, SPTIE)
EECTL(CCIE, CBEIE)
FCTL(CCIE, CBEIE)
PWMSDN (PWMIE)
CRGINT(LOCKIE)
CRGINT (SCMIE)
PBCTL(PBOVI)
PTPIF (PTPIE)
IBCR (IBIE)
$C8
$C6
$C4
$C0
$BE
$BA
$8C
$B8
$8E