MC9S12A128 MOTOROLA [Motorola, Inc], MC9S12A128 Datasheet
MC9S12A128
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MC9S12A128 Summary of contents
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... Motorola was negligent regarding the design or manufacture of the part. MC9S12A128 Device Guide V01.01 ...
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... APRIL 12 APRIL V01.01 2002 2002 For additional information, refer to the MC9S12A128 8-Bit Microcontroller Unit Mask Set Errata (Motorola document order number, 9S12A128MSE1). The errata can be found on the World Wide Web at: http://www.motorola.com/semiconductors/ 2 Author Description of Changes Initial release Replaced document order number with version except for cover ...
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... PE4 / ECLK — Port E I/O Pin 2.3.17 PE3 / LSTRB / TAGLO — Port E I/O Pin 2.3.18 PE2 / R/W — Port E I/O Pin 2.3.19 PE1 / IRQ — Port E Input Pin 2.3.20 PE0 / XIRQ — Port E Input Pin 2.3.21 PH7 / KWH7 — Port H I/O Pin MC9S12A128 Device Guide — V01.01 3 ...
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... MC9S12A128 Device Guide — V01.01 2.3.22 PH6 / KWH6 — Port H I/O Pin 2.3.23 PH5 / KWH5 — Port H I/O Pin 2.3.24 PH4 / KWH4 — Port H I/O Pin 2.3.25 PH3 / KWH3 / SS1 — Port H I/O Pin 2.3.26 PH2 / KWH2 / SCK1 — Port H I/O Pin 2.3.27 PH1 / KWH1 / MOSI1 — Port H I/O Pin .31 2.3.28 PH0 / KWH0 / MISO1 — ...
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... Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Section 5 Resets and Interrupts 5.1 Overview 5.2 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 5.2.1 Vector Table 5.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.3.1 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.3.2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Section 6 HCS12 Core Block Description Section 7 Clock and Reset Generator (CRG) Block Description — Core Power Pins SS2 MC9S12A128 Device Guide — V01.01 5 ...
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... MC9S12A128 Device Guide — V01.01 7.1 Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.1.1 XCLKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Section 8 Enhanced Capture Timer (ECT) Block Description Section 9 Analog to Digital Converter (ATD) Block Description Section 10 Inter-IC Bus (IIC) Block Description Section 11 Serial Communications Interface (SCI) Block Description Section 12 Serial Peripheral Interface (SPI) Block Description ...
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... NVM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 A.3.2 NVM Reliability A.4 Voltage Regulator A.5 Reset, Oscillator and PLL .74 A.5.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 A.5.2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 A.5.3 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 A.6 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 A.6.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 A.6.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 A.7 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 A.7.1 General Muxed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Appendix B Package Information B.1 General .87 B.2 112-Pin LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 B.3 80-Pin QFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 MC9S12A128 Device Guide — V01.01 7 ...
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... MC9S12A128 Device Guide — V01.01 8 ...
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... List of Figures Figure 1-1 MC9S12A128 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 1-2 MC9S12A128 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 2-1 Pin Assignments in 112-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 2-2 Pin Assignments in 80-Pin QFP for MC9S12A128 . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 2-3 PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 3-1 Clock Connections .39 Figure 18-1 Recommended PCB Layout 112 LQFP Figure 18-2 Recommended PCB Layout for 80 QFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure A-1 ATD Accuracy Definitions ...
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... MC9S12A128 Device Guide — V01.01 10 ...
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... Document References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 1-1 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Table 1-2 Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 1-3 Memory Size Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 2-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 2-2 MC9S12A128 Power and Ground Connection Summary . . . . . . . . . . . . . . . . . . .37 Table 4-1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 5-1 Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table A-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table A-2 ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table A-3 ESD and Latch-Up Protection Characteristics ...
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... MC9S12A128 Device Guide — V01.01 12 ...
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... Preface The Device User Guide provides information about the MC9S12A128 device made up of standard HCS12 blocks and the HCS12 processor core. This document is part of the customer documentation. A complete set of device manuals also includes the CPU12 Reference Manual (Motorola order number, CPU12RM/AD) and all the individual Block Guides of the implemented modules ...
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... MC9S12A128 Device Guide — V01.01 14 ...
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... Inter-IC Bus. System resource mapping, clock generation, interrupt control and bus interfacing are managed by the System Integration Module (SIM). The MC9S12A128 has full 16-bit data paths throughout. However, the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems ...
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... MC9S12A128 Device Guide — V01.01 • Two 8-channel Analog-to-Digital Converters – 10-bit resolution – External conversion trigger capability • Enhanced Capture Timer – 16-bit main counter with 7-bit prescaler – 8 programmable input capture or output compare channels – Two 8-bit or one 16-bit pulse accumulators • ...
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... Special Single-Chip Mode with active Background Debug Mode – Special Test Mode (Motorola use only) – Special Peripheral Mode (Motorola use only) Low power modes • Stop Mode • Pseudo Stop Mode • Wait Mode MC9S12A128 Device Guide — V01.01 17 ...
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... MC9S12A128 Device Guide — V01.01 1.4 Block Diagram Figure 1-1 shows a block diagram of the MC9S12A128 device. 18 ...
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... Internal Logic 2.5V I/O Driver 5V VDD1,2 VDDX VSS1,2 VSSX A/D Converter 5V & PLL 2.5V Voltage Regulator Reference VDDPLL VDDA VSSPLL VSSA Voltage Regulator 5V & I/O VDDR VSSR MC9S12A128 Device Guide — V01.01 VRH VRH ATD0 ATD1 VRL VRL VDDA VDDA VSSA VSSA AN0 PAD00 AN0 AN1 PAD01 ...
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... Device Memory Map Table 1-1 Figure 1-2 and show the device memory map of the MC9S12A128 after reset. Note that after reset the bottom 1K of the EEPROM ($0000 - $03FF) are hidden by the register space. Address $0000 – $0017 CORE (Ports Modes, Inits, Test) $0018 – ...
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... The address does not show the map after reset, but a useful map. After reset the map is: $0000 – $03FF: Register Space $0000 – $1FFF: 8K RAM $0000 – $07FF: 2K EEPROM (not visible) $2000 – $3FFF: 8K Flash MC9S12A128 Device Guide — V01.01 $0000 1K Register Space $03FF Mappable to any 2K Boundary ...
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... MC9S12A128 Device Guide — V01.01 1.6 Part ID Assignments The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses $001A and $001B after reset). The read-only value is a unique part ID for each revision of the chip. part ID number. Device MC9S12A128 NOTES: 1. The coding is as follows: ...
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... It is built from the signal description sections of the Block Guides of the individual IP blocks on the device. 2.1 Device Pinout The MC9S12A128 is available in a 112-pin low profile quad flat pack (LQFP) and is also available in a 80-pin quad flat pack (QFP). Most pins perform two or more functions, as described in the Figure 2-1 Signal Descriptions ...
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... MC9S12A128 Device Guide — V01.01 SS1/PWM3/KWP3/PP3 1 SCK1/PWM2/KWP2/PP2 2 MOSI1/PWM1/KWP1/PP1 3 MISO1/PWM0/KWP0/PP0 4 XADDR17/PK3 5 XADDR16/PK2 6 XADDR15/PK1 7 XADDR14/PK0 8 IOC0/PT0 9 IOC1/PT1 10 IOC2/PT2 11 IOC3/PT3 12 VDD1 13 VSS1 14 IOC4/PT4 15 IOC5/PT5 16 IOC6/PT6 17 IOC7/PT7 18 XADDR19/PK5 19 XADDR18/PK4 20 KWJ1/PJ1 21 KWJ0/PJ0 22 MODC/TAGHI/BKGD 23 ADDR0/DATA0/PB0 24 ADDR1/DATA1/PB1 25 ADDR2/DATA2/PB2 26 ADDR3/DATA3/PB3 27 ADDR4/DATA4/PB4 28 Figure 2-1 Pin Assignments in 112-Pin LQFP 24 MC9S12A128 Signals shown in Bold are not available on the 80 Pin Package ...
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... IOC1/PT1 6 IOC2/PT2 7 IOC3/PT3 8 VDD1 9 VSS1 10 IOC4/PT4 11 IOC5/PT5 12 IOC6/PT6 13 IOC7/PT7 14 MODC/TAGHI/BKGD 15 ADDR0/DATA0/PB0 16 ADDR1/DATA1/PB1 17 ADDR2/DATA2/PB2 18 ADDR3/DATA3/PB3 19 ADDR4/DATA4/PB4 20 Figure 2-2 Pin Assignments in 80-Pin QFP for MC9S12A128 MC9S12A128 Device Guide — V01.01 60 VRH 59 VDDA 58 PAD07/AN07/ETRIG0 57 PAD06/AN06 56 PAD05/AN05 55 PAD04/AN04 54 PAD03/AN03 53 PAD02/AN02 52 PAD01/AN01 51 PAD00/AN00 MC9S12A128 50 VSS2 49 VDD2 48 PA7/ADDR15/DATA15 47 ...
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... MC9S12A128 Device Guide — V01.01 2.2 Signal Properties Summary Table 2-1 summarizes the pin functionality. Signals shown in bold are not available in the 80 pin package. Pin Name Pin Name Pin Name Function 1 Function 2 Function 3 EXTAL — XTAL — RESET — TEST — VREGEN — ...
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... MC9S12A128 Device Guide — V01.01 Description Port J I/O, Interrupt, SCL of IIC Port J I/O, Interrupt, SDA of IIC Port J I/O, Interrupts Port K I/O, Emulation Chip Select, ROM On Enable Port K I/O, Extended Addresses Port M I/O Port M I/O Port M I/O, SCK of SPI0 ...
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... MC9S12A128 Device Guide — V01.01 2.3 Detailed Signal Descriptions 2.3.1 EXTAL, XTAL — Oscillator Pins EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived from the EXTAL input frequency. XTAL is the crystal output. 2.3.2 RESET — External Reset Pin An active low bidirectional control signal, it acts as an input to initialize the MCU to a known start-up state, and an output when an internal MCU function causes a reset ...
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... PE7 is a general purpose input or output pin. During MCU expanded modes of operation, the NOACC signal, when enabled, is used to indicate that the current bus cycle is an unused or “free” cycle. This signal will assert when the CPU is not using the bus. MC9S12A128 Device Guide — V01.01 29 ...
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... MC9S12A128 Device Guide — V01.01 The XCLKS input selects between an external clock or oscillator configuration. The state of this pin is latched at the rising edge of RESET. If the input is a logic low the EXTAL pin is configured for an external clock drive. If input is a logic high an oscillator circuit is configured on EXTAL and XTAL. Since this pin is an input with a pull-up device, if the pin is left floating, the default configuration is an oscillator circuit on EXTAL and XTAL ...
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... PH0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of the Serial Peripheral Interface 1 (SPI1). MC9S12A128 Device Guide — V01.01 31 ...
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... MC9S12A128 Device Guide — V01.01 2.3.29 PJ7 / KWJ7 / SCL — PORT J I/O Pin 7 PJ7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as the serial clock pin SCL of the IIC module. 2.3.30 PJ6 / KWJ6 / SDA — PORT J I/O Pin 6 PJ6 is a general purpose input or output pin ...
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... PP3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 3 output. It can be configured as slave select pin SS of the Serial Peripheral Interface 1 (SPI1). MC9S12A128 Device Guide — V01.01 33 ...
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... MC9S12A128 Device Guide — V01.01 2.3.47 PP2 / KWP2 / PWM2 / SCK1 — Port P I/O Pin 2 PP2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 2 output. It can be configured as serial clock pin SCK of the Serial Peripheral Interface 1 (SPI1). ...
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... PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0] PT7-PT0 are general purpose input or output pins. They can be configured as input capture or output compare pins IOC7-IOC0 of the Enhanced Capture Timer (ECT). 2.4 Power Supply Pins MC9S12A128 power and ground pins are described below. NOTE: All V pins must be connected together in the application. ...
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... MC9S12A128 Device Guide — V01.01 2.4 DD1 DD2 SS1 Power is supplied to the MCU through V short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. This 2.5V supply is derived from the internal voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is turned off tied to ground ...
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... Table 2-2 MC9S12A128 Power and Ground Connection Summary Pin Number Nominal Mnemonic Voltage 112-pin QFP V 13, 65 2.5 V DD1 14 SS1 5.0 V DDR SSR V 107 5.0 V DDX V 106 0 V SSX V 83 5.0 V DDA SSA 5 ...
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... MC9S12A128 Device Guide — V01.01 38 ...
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... Consult the HCS12 Clock and Reset Generator (CRG) Block Guide (Motorola document order number, S12CRGV3/D) for details on clock generation. EXTAL CRG XTAL 1/2 core clock bus clock oscillator clock Figure 3-1 Clock Connections MC9S12A128 Device Guide — V01.01 BDM S12_CORE Flash RAM EEPROM ECT ATD0, 1 PWM SCI0, SCI1 ...
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... MC9S12A128 Device Guide — V01.01 40 ...
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... Section 4 Modes of Operation 4.1 Overview Eight possible modes determine the operating configuration of the MC9S12A128. Each mode has an associated default memory map and external bus configuration. Three low power modes exist for the device. 4.2 Modes of Operation The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during ...
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... MC9S12A128 Device Guide — V01.01 even located in an external slow memory device. The PE6/MODB/IPIPE1 and PE5/MODA/IPIPE0 pins act as high-impedance mode select inputs during reset. The following paragraphs discuss the default bus setup and describe which aspects of the bus can be changed after reset on a per mode basis. ...
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... PE2 can be left as a general purpose I/O pin. 4.2.1.4 Internal Visibility Internal visibility is available when the MCU is operating in expanded wide modes or emulation narrow mode not available in single-chip, peripheral or normal expanded narrow modes. Internal visibility is enabled by setting the IVIS bit in the MODE register. MC9S12A128 Device Guide — V01.01 43 ...
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... MC9S12A128 Device Guide — V01. internal access is made while E, R/W, and LSTRB are configured as bus control outputs and internal visibility is off (IVIS=0), E will remain low for the cycle, R/W will remain high, and address, data and the LSTRB pins will remain at their previous state. ...
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... Since the mode control register is not accessible in peripheral mode, the only way to change to another mode is to reset the MCU into a different mode. Background debugging should not be used while the MCU is in special peripheral mode MC9S12A128 Device Guide — V01.01 45 ...
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... MC9S12A128 Device Guide — V01.01 as internal bus conflicts between BDM and the external master can cause improper operation of both functions. 4.3 Security The device will make available a security feature preventing the unauthorized read and write of the memory contents. This feature allows: • ...
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... Low Power Modes Consult the respective Block Guide for information on the module behavior in Stop, Pseudo Stop, and Wait Mode. MC9S12A128 Device Guide — V01.01 47 ...
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... MC9S12A128 Device Guide — V01.01 48 ...
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... SPI0 I-Bit SCI0 I-Bit SCI1 I-Bit ATD0 I-Bit ATD1 I-Bit Port J I-Bit Port H I-Bit I-Bit MC9S12A128 Device Guide — V01.01 HPRIO Value Local Enable to Elevate None PLLCTL (CME, SCME) COP rate select None None None IRQCR (IRQEN) $F2 CRGINT (RTIE) $F0 TIE (C0I) ...
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... Refer to the HCS12 Core User Guide (Motorola document order number HCS12COREUG/D) for mode dependent pin configuration of port and K out of reset. Refer to the MC9S12A128 Port Integration Module (PIM) Block Guide (Motorola document order number, S12A128PIMV1/D) for reset configurations of all peripheral module ports. ...
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... Section 9 Analog to Digital Converter (ATD) Block Description There are two Analog to Digital Converters (ATD1 and ATD0) implemented on the MC9S12A128. Consult the HCS12 10-Bit, 8-Channel Analog-to-Digital Converter (ATD) Block Guide (Motorola document order number, S12ATD10B8CV2/D) for information about each Analog to Digital Converter module ...
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... S12SCIV2/D) for information about each Serial Communications Interface module. Section 12 Serial Peripheral Interface (SPI) Block Description There are two Serial Peripheral Interfaces (SPI1 and SPI0) implemented on MC9S12A128. Consult the HCS12 Serial Peripheral Interface (SPI) Block Guide (Motorola document order number, S12SPIV2/D) for information about each Serial Peripheral Interface module. ...
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... Section 17 Port Integration Module (PIM) Block Description Consult the MC9S12A128 Port Integration Module (PIM) Block Guide (Motorola document order number, S12A128PIMV1/D) for information about the Port Integration Module. Section 18 Voltage Regulator (V Consult the HCS12 Voltage Regulator Block Guide (Motorola document order number, S12VREGV1/D) for information about the dual output linear voltage regulator ...
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... MC9S12A128 Device Guide — V01.01 The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the MCU itself. The following rules must be observed: • Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins (C1 - C6). ...
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... Figure 18-1 Recommended PCB Layout 112 LQFP VSSX VDD1 C1 VSS1 VSSR VDDR MC9S12A128 Device Guide — V01.01 VSSA C3 Q1 VSSPLL VDDPLL R1 VDDA VSS2 C2 VDD2 55 ...
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... MC9S12A128 Device Guide — V01.01 Figure 18-2 Recommended PCB Layout for 80 QFP VDD1 C1 VSS1 56 VSSA VSSX VSSR VDDR Q1 VSSPLL VDDPLL R1 C3 VDDA VSS2 C2 VDD2 ...
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... D: Those parameters are derived mainly from simulations. A.1.2 Power Supply The MC9S12A128 utilizes several pins to supply power to the I/O ports, A/D converter, oscillator and PLL as well as the digital core. The pair supplies the A/D converter and the resistor ladder of the internal voltage regulator. ...
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... DD5 and V unless otherwise noted. SSR SSX , V and used for V DD1 DD2 DDPLL SS and V pins MC9S12A128 Device Guide — V01.01 supplies also the internal voltage DDR , V supply the oscillator DDPLL SSPLL , V and used DDA DDR DDX SS5 , V and V pins ...
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... V (3) (4) and and V SSX DDX SSR and V . SSPLL DDPLL , but not clamped high. This pin must be tied low in applications. MC9S12A128 Device Guide — V01. range during instantaneous and DD > greater than I in DD5 SS5 DD5 (1) Min Max V – ...
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... C Machine Model (MM Charge Device Model (CDM) Latch-up Current 125 positive negative Latch-up Current positive negative Description Rating Symbol MC9S12A128 Device Guide — V01.01 Symbol Value R1 1500 C 100 — 3 — 200 — 3 — 3 — ...
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... T A and the junction temperature T A.1.8 Power Dissipation and Thermal Table A-4 Operating Conditions Symbol V DD5 DDPLL DDA VDDX SSA VSSX f osc f bus ( MC9S12A128 Device Guide — V01.01 . For power dissipation J Characteristics. Min Typ Max 4.5 5 5.25 2.35 2.5 2.75 2.25 2.5 2.75 –0.1 0 0.1 –0.1 0 0.1 0.5 — 16 0.5 — ...
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... P D INT DDPLL DDPLL DSON ----------- - for outputs driven low ; DSON – DD5 OH = ----------------------------------- - for outputs driven high ; I OH MC9S12A128 Device Guide — V01. can DDA DDA 2 and V . DDX DDR 62 ...
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... INT DDR DDR DDA Table A-7 and not the overall current flowing into DSON Symbol ( MC9S12A128 Device Guide — V01.01 V DDA , which DDR 2 and V . DDX DDR (1) Min Typ Max — — 54 — — 41 — — 51 — ...
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... HYS PUL I PUH I PDH I PDL ICS I ICP (3) t PULSE (3) t PULSE MC9S12A128 Device Guide — V01.01 Min Typ Max 0.65*V — — DD5 V + 0.3 — — DD5 0.35*V — — DD5 V – 0.3 — — SS5 — 250 — –2.5 — ...
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... C I DDPS 105 C – DDS 85 C “C” Temp Option 100 C 105 can be assumed J A MC9S12A128 Device Guide — V01.01 Min Typ Max — — 65 — — 40 — — 5 — 370 — 400 500 — ...
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... V – ATDCLK (2) N Clock Cycles CONV10 T ATDCLK CONV10 (2) N Clock Cycles CONV8 T ATDCLK CONV8 =5.0 Volts REF I REF Table A-6 MC9S12A128 Device Guide — V01.01 Min Typ Max V — SSA DDA V /2 — V DDA DDA 4.50 5.00 5.25 0.5 — 2.0 14 — — ...
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... Total Input Capacitance 2 T Non Sampling Sampling 3 C Disruptive Analog Input Current 4 C Coupling Ratio positive current injection 5 C Coupling Ratio negative current injection MC9S12A128 Device Guide — V01.01 1024 * ( INS INN and $000 for values less than RH Symbol Min ...
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... LSB DNL INL AE Figure A- – – DNL i ------------------------- - 1 = – 1LSB n V – n INL n DNL i -------------------- - 1LSB MC9S12A128 Device Guide — V01.01 Min Typ Max — 5 — –1 1 –2.5 1.5 2.5 –3 2.0 3 — 20 — –0.5 — 0.5 –1.0 0.5 1.0 –1.5 1.0 1 – Unit ...
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... Absolute Error Boundary i Ideal Transfer Curve 10-Bit Transfer Curve 8-Bit Transfer Curve 40 45 5055 5060 5065 5070 5075 5080 MC9S12A128 Device Guide — V01.01 5085 5090 5095 5100 5105 5110 5115 5120 Table A-10. $FF $FE $ Vin mV ...
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... Burst programming is more than 2 times faster than single word programming. Table A-11 are calculated for maximum ------------------------ - + 25 swpgm f NVMOP ------------------------ - + 9 bwpgm f NVMOP brpgm swpgm bwpgm MC9S12A128 Device Guide — V01.01 NVMOP and 2MHz. NVMOP bus 1 ----------- - f bus 1 ----------- - f bus and 70 ...
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... Symbol f NVMOSC f NVMBUS f NVMOP t swpgm (4) t bwpgm 4 t brpgm t era t mass t check t check Programming- A.3.1.4 Mass Erase MC9S12A128 Device Guide — V01.01 cyc Min Typ Max (1) 0.5 — — 150 — 200 (2) (3) — 46 74.5 (2) (3) — 20.4 31 (2) (3) — 678.4 1035.5 ...
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... EEPROM cycling performance is 10,000 cycles at –40 to +85 C. Data retention is specified for 10 years. NOTE: These figures are provided for commercial quality levels not automotive. Table A-12 are target values and subject to further extensive NVM Array MC9S12A128 Device Guide — V01.01 Data Retention Cycles Lifetime 1000 10 years 10,000 ...
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... The on-chip voltage regulator is intended to supply the internal logic and oscillator circuits. No external DC load is allowed. Table A-13 Voltage Regulator Recommended Load Capacitances Rating Load Capacitance on V DD1, 2 Load Capacitance on V DDPLL MC9S12A128 Device Guide — V01.01 Symbol Min Typ C — 220 LVDD C — ...
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... PORR V PORA PW RSTL n RST PW IRQ t WRS are derived from the V PORA no valid oscillation is detected, the MCU will start using the internal self . uposc RSTL MC9S12A128 Device Guide — V01.01 Min Typ Max — — 2.07 0.97 — — 2 — — 192 — 196 20 — ...
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... D Input Capacitance (EXTAL, XTAL pins) DC Operating Bias in Colpitts Configuration EXTAL Pin NOTES 4MHz 22pF. osc 2. Maximum value is for extreme cases using high Q, low frequency crystals 3. XCLKS =0 during reset MC9S12A128 Device Guide — V01.01 Symbol Min f 0.5 OSC I 100 OSC n 4100 ...
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... The VCO Gain at the desired VCO output frequency is approximated by: The phase detector relationship is given by the current in tracking mode DDPLL Phase K Detector f cmp Loop Divider 1 synr+1 A-16 – 1 vco --------------------------- - – MC9S12A128 Device Guide — V01. VCO f vco ...
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... Table A-16 are dependant on PLL operational settings and external Figure A-2. With each transition of the clock f is measured and input voltage to the VCO is adjusted ref MC9S12A128 Device Guide — V01.01 ref 0 0.9 Figure , the cmp A-3. 77 ...
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... This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the effect of the jitter to a large extent minN t maxN Figure A-3 Jitter Definitions max min = max 1 – ---------------------- - , 1 – ---------------------- - nom ------- - + MC9S12A128 Device Guide — V01.01 N nom N 78 ...
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... 50MHz: REFDV = #$03, SYNR = #$018 4.7nF 470pF, VCO MC9S12A128 Device Guide — V01.01 Min Typ Max 1 — 5.5 8 — — — 1.5 0.5 — 2.5 6 — 8 — 0.5 — — 0.3 — — ...
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... LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure A-6 SPI Master Timing (CPHA = BIT LSB BIT BIT BIT MC9S12A128 Device Guide — V01.01 Table LSB OUT LSB IN MASTER LSB OUT PORT DATA A-17. 80 ...
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... Table A-18 BIT BIT MC9S12A128 Device Guide — V01.01 1 Min Typ Max DC — — 2048 1 2 — — — — 1024 t — bus bus 25 — — ...
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... BIT Symbol sck t lead t lag t wsck dis MC9S12A128 Device Guide — V01. SLAVE LSB OUT LSB IN Min Typ Max DC — — 2048 1 — — 1 — — — — cyc 25 — ...
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... A.7.1 General Muxed Bus Timing The expanded bus timings are highly dependent on the load conditions. The timing parameters shown assume a balanced load across all outputs. MC9S12A128 Device Guide — V01.01 Figure A-9 with the actual timing 83 ...
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... PA, PB Addr/Data data (write) PA Non-Multiplexed Addresses PK5:0 20 ECS PK7 24 R/W PE2 27 LSTRB PE3 30 NOACC PE7 33 IPIPO0 IPIPO1, PE6,5 Figure A-9 General External Bus Timing MC9S12A128 Device Guide — V01. addr addr data 14 13 data ...
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... RWD – RWD RWV t RWH t LSD – LSD LSV t LSH t NOD – NOD NOV MC9S12A128 Device Guide — V01.01 Min Typ Max 0 — 25.0 40 — — 19 — — 19 — — — — — — 2 — — 7 — — ...
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... LOAD Symbol t NOH t P0D – P0D P0V P1D EH P1V t P1V where N=0,1 depending on the number of clock stretches. cyc MC9S12A128 Device Guide — V01.01 Min Typ Max 2 — — 2 — — — 2 — — — Unit ...
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... Appendix B Package Information B.1 General This section provides the physical dimensions of the MC9S12A128 packages. MC9S12A128 Device Guide — V01.01 87 ...
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... MC9S12A128 Device Guide — V01.01 B.2 112-Pin LQFP Package 0. PIN 1 112 IDENT 1 VIEW 0.050 C1 VIEW AB Figure B-1 112-Pin LQFP Mechanical Dimensions (Case no. 987) 88 0. TIPS VIEW AB 2 0.10 T 112X SEATING PLANE ...
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... AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM K MATERIAL CONDITION. DAMBAR CANNOT Q BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MC9S12A128 Device Guide — V01. -A-,-B-,-D- DETAIL 0.20 ...
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... MC9S12A128 Device Guide — V01.01 90 ...
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... User Guide End Sheet MC9S12A128 Device Guide — V01.01 91 ...
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... MC9S12A128 Device Guide — V01.01 92 FINAL PAGE OF 92 PAGES ...