MC9S12A128 MOTOROLA [Motorola, Inc], MC9S12A128 Datasheet - Page 41
![no-image](/images/no-image-200.jpg)
MC9S12A128
Manufacturer Part Number
MC9S12A128
Description
Microcontroller unit (MCU)
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC9S12A128.pdf
(92 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12A128BCFU
Manufacturer:
SIEMENS
Quantity:
3 274
Company:
Part Number:
MC9S12A128BCFU
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12A128BCFU
Manufacturer:
FREESCALE
Quantity:
20 000
Company:
Part Number:
MC9S12A128BCFUE
Manufacturer:
EEMB
Quantity:
100
Company:
Part Number:
MC9S12A128BCPV
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MC9S12A128CFUE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12A128CFUE
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
MC9S12A128CPV
Manufacturer:
FREESCALE
Quantity:
20 000
Company:
Part Number:
MC9S12A128CPVE
Manufacturer:
FREESCALE
Quantity:
2 390
Part Number:
MC9S12A128CPVE
Manufacturer:
FREESCALE
Quantity:
20 000
Section 4 Modes of Operation
4.1 Overview
Eight possible modes determine the operating configuration of the MC9S12A128. Each mode has an
associated default memory map and external bus configuration.
Three low power modes exist for the device.
4.2 Modes of Operation
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during
reset
mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA
pins are latched into these bits on the rising edge of the reset signal.
There are two basic types of operating modes:
A system development and debug feature, background debug mode (BDM), is available in all modes. In
special single-chip mode, BDM is active immediately after reset.
Some aspects of Port E are not mode dependent. Bit 1 of Port E is a general purpose input or the IRQ
interrupt input. IRQ can be enabled by bits in the CPU’s condition codes register but it is inhibited at reset
so this pin is initially configured as a simple input with a pull-up. Bit 0 of Port E is a general purpose input
or the XIRQ interrupt input. XIRQ can be enabled by bits in the CPU’s condition codes register but it is
inhibited at reset so this pin is initially configured as a simple input with a pull-up. The ESTR bit in the
EBICTL register is set to one by reset in any user mode. This assures that the reset vector can be fetched
1. Normal modes: Some registers and bits are protected against accidental changes.
2. Special modes: Allow greater access to protected control registers and bits for special purposes such
(Table
as testing.
MODC
0
0
0
0
1
1
1
1
4-1). The MODC, MODB, and MODA bits in the MODE register show the current operating
MODB
0
0
1
1
0
0
1
1
MODA
0
1
0
1
0
1
0
1
Table 4-1 Mode Selection
Special Single Chip, BDM allowed and ACTIVE. BDM is allowed in all
other modes but a serial command is required to make BDM active.
Emulation Expanded Narrow, BDM allowed
Special Test (Expanded Wide), BDM allowed
Emulation Expanded Wide, BDM allowed
Normal Single Chip, BDM allowed
Normal Expanded Narrow, BDM allowed
Peripheral; BDM allowed but bus operations would cause bus conflicts
(must not be used)
Normal Expanded Wide, BDM allowed
Mode Description
MC9S12A128 Device Guide — V01.01
41