FAN53168MTC FAIRCHILD [Fairchild Semiconductor], FAN53168MTC Datasheet - Page 3

• Manufacturer Part Number: FAN53168MTC
• Description: 6-Bit VID Controlled 2-4 Phase DC-DC Controller
• Manufacturer: FAIRCHILD [Fairchild Semiconductor]

PRODUCT SPECIFICATION
Pin Configuration
Pin Definitions
REV. 1.0.0 6/9/03
Number Pin Name Pin Function Description
20–23
24–27
1–6
Pin
10
11
12
13
14
15
16
17
18
19
28
7
8
9
RAMPADJ PWM Current Ramp Adjust. An external resistor to Vcc will adjust the amplitude of the
CSCOMP Current Sense Compensation node. Output of the current sense amplifier. This pin is
PWM[4:1] PWM Outputs. CMOS outputs for driving external gate drivers such as the FAN53418.
VID[4:0],
PWRGD
CSSUM
SW[4:1]
CSREF
FBRTN
DELAY
COMP
ILIMIT
VID5
GND
VCC
EN
FB
RT
VID Inputs. Determines the output voltage via the internal DAC. These inputs are
compliant to VRM10/VRD10 specifications for static and dynamic operation. All have
internal pull-ups so leaving them open results in logic high. Leaving VID[4:0] open results
in a “No CPU” condition disabling the PWM outputs.
Feedback Return. Error Amp and DAC reference point.
Feedback Input. Inverting input for Error Amp this pin is used for external compensation.
Can also be used to introduce DC offset voltage to the output.
Error Amp Output. This pin is used for external compensation.
Power Good Output. This is an open-drain output that asserts when the output voltage is
within the specified tolerance. It is expected to be pulled up to an external voltage rail.
Output Enable. This is a dual-function pin. It allows for an external open-drain drain logic
signal to enable the output PWM.
Soft-start and Current Limit Delay. An external resistor and capacitor sets the soft-start
ramp rate and the over-current latch off delay.
Switching Frequency Adjust. This pin adjusts the output PWM switching frequency via
an external resistor.
internal PWM ramp.
Current Limit Adjust. An external resistor sets the current limit threshold for the regulator
circuit. This pin is internally pulled low when EN is low or the UVLO circuit is active.
Current Sense Return. Inverting input of the current sense amp. Sense point for the
output voltage used for OVP, and PWRGD.
Current Sense Summing node. Non-inverting input of the current sense amp.
used for droop compensation, a current loop reponse.
Analog Chip Ground. Signal ground for the chip
Phase Current Sense/Balance inputs. Phase-to-phase current sense and balancing
inputs. Unused phases should be left open.
Unused phases should be grounded.
Chip Power. Bias supply for the chip. Connect directly to a +12V supply. Bypass with a
1 µ F MLCC capacitor.
RAMPADJ
PWRGD
FBRTN
DELAY
COMP
VID4
VID3
VID2
VID1
VID0
VID5
EN
RT
FB
10
11
12
13
14
1
2
3
4
5
6
7
8
9
FAN53168
TSSOP-28
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
PWM1
PWM2
PWM3
PWM4
SW1
SW2
SW3
SW4
GND
CSCOMP
CSSUM
CSREF
ILIMIT
FAN53168
3